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[partial-reconfig] Problems with MAP in Active phase
Hello All,
I am trying to setup DPR for a simple design.
The design contains 2 modules (admxrc_if and incrementer).
I have done the initial budgeting phase and generated the NGD file
for the top level. I am getting the following error multiple times
while running 'map' on the admxrc_if module. This module interfaces with the
PCI interface supplied by the Alpha-Data Virtex 2 (v3000) board that I am
using.
ERROR:MapLib:492 - Create a dummy tbuf in the context connected to signal
lbterm_l_OBUF with a location constraint to a single site.
lbterm_l is an output signal from my design. The same error is present for every
output signal from the top level design.
I suspect the problem is due to a mistake in the UCF file or with my synthesis
settings. I am using XST for synthesis. I have disabled the IO buffer inserting
in the modules as mentioned in xapp290.
I am attaching the UCF file for reference.
I hope you'll be able to help me with this issue.
An early response will be highly appreciated.
Thanking you in advance.
Best Regards,
Devadutt
Master's student
Computer Science and Engineering
Indian Institute of Technology - Delhi
##########################################################
# #
# Recommended pin performance attributes #
# #
##########################################################
NET "ld(*" FAST;
NET "la(*" FAST;
NET "lreadyi_l" FAST;
NET "lbterm_l" FAST;
##########################################################
# #
# Timing specifications #
# #
# All delays in ns #
# #
# Local bus clock: 33MHz max #
# #
##########################################################
NET "lclk" TNM_NET = "TNM_LCLK";
TIMEGRP "LCLK_PAD" = "pads(lclk)";
TIMEGRP "LD_PADS" = "pads(ld(*))";
TIMEGRP "LA_PADS" = "pads(la(*))";
TIMEGRP "LADS_PAD" = "pads(lads_l)";
TIMEGRP "LWRITE_PAD" = "pads(lwrite)";
TIMEGRP "LBLAST_PAD" = "pads(lblast_l)";
TIMEGRP "LBTERM_PAD" = "pads(lbterm_l)";
TIMEGRP "LREADY_PAD" = "pads(lreadyi_l)";
TIMEGRP "FHOLDA_PAD" = "pads(fholda)";
TIMEGRP "LCTL_PADS" = "LADS_PAD":
"LWRITE_PAD":
"LBLAST_PAD":
"LBTERM_PAD":
"LREADY_PAD":
"FHOLDA_PAD";
# Clock distribution & reset
NET "lclk" MAXDELAY = 3.0ns;
NET "lreseto_l" MAXDELAY = 30.0ns;
# Internal timing
TIMESPEC TS_LCLK_FFS_FFS = PERIOD "TNM_LCLK" 30.0ns HIGH 50%;
# FPGA clock-to-output
TIMEGRP "LD_PADS" OFFSET = OUT 22.0ns AFTER "lclk";
TIMEGRP "LCTL_PADS" OFFSET = OUT 17.0ns AFTER "lclk";
# FPGA setup
TIMEGRP "LD_PADS" OFFSET = IN 15.0ns BEFORE "lclk";
TIMEGRP "LA_PADS" OFFSET = IN 14.2ns BEFORE "lclk";
TIMEGRP "LCTL_PADS" OFFSET = IN 14.0ns BEFORE "lclk";
# Start of Constraints extracted by Floorplanner from the Design
#AREA_GROUP "AG_inc" RANGE = SLICE_X0Y127:SLICE_X19Y0 ;
AREA_GROUP "AG_inc" RANGE = SLICE_X0Y127:SLICE_X19Y0, TBUF_X0Y127:TBUF_X18Y0, RAMB16_X0Y0:RAMB16_X0Y15, MULT18X18_X0Y0:MULT18X18_X0Y15 ;
INST "inc" AREA_GROUP = "AG_inc" ;
#AREA_GROUP "AG_admxrcif" RANGE = SLICE_X20Y127:SLICE_X111Y0 ;
AREA_GROUP "AG_admxrcif" RANGE = SLICE_X20Y127:SLICE_X111Y0, TBUF_X20Y127:TBUF_X110Y0, RAMB16_X1Y0:RAMB16_X1Y15, RAMB16_X2Y0:RAMB16_X2Y15, RAMB16_X3Y0:RAMB16_X3Y15, RAMB16_X4Y0:RAMB16_X4Y15, RAMB16_X5Y0:RAMB16_X5Y15, MULT18X18_X1Y0:MULT18X18_X1Y15, MULT18X18_X2Y0:MULT18X18_X2Y15, MULT18X18_X3Y0:MULT18X18_X3Y15, MULT18X18_X4Y0:MULT18X18_X4Y15, MULT18X18_X5Y0:MULT18X18_X5Y15 ;
INST "admxrcif" AREA_GROUP = "AG_admxrcif" ;
# Assigning Locations for the bus macros.
# bm_toinc1,bm_toinc2,bm_frominc1,bm_frominc2 are 16 bit bus macros built on
# the 4 bit bus macros provided by Xilinx.
INST bm_incsig LOC = TBUF_X16Y45;
INST bm_toinc1/bus1 LOC = TBUF_X16Y37;
INST bm_toinc1/bus2 LOC = TBUF_X16Y35;
INST bm_toinc1/bus3 LOC = TBUF_X16Y33;
INST bm_toinc1/bus4 LOC = TBUF_X16Y31;
INST bm_toinc2/bus1 LOC = TBUF_X16Y29;
INST bm_toinc2/bus2 LOC = TBUF_X16Y27;
INST bm_toinc2/bus3 LOC = TBUF_X16Y25;
INST bm_toinc2/bus4 LOC = TBUF_X16Y23;
INST bm_frominc1/bus1 LOC = TBUF_X16Y67;
INST bm_frominc1/bus2 LOC = TBUF_X16Y65;
INST bm_frominc1/bus3 LOC = TBUF_X16Y63;
INST bm_frominc1/bus4 LOC = TBUF_X16Y61;
INST bm_frominc2/bus1 LOC = TBUF_X16Y59;
INST bm_frominc2/bus2 LOC = TBUF_X16Y57;
INST bm_frominc2/bus3 LOC = TBUF_X16Y55;
INST bm_frominc2/bus4 LOC = TBUF_X16Y53;
AREA_GROUP "AG_inc" MODE=RECONFIG ;
NET "lwrite" LOC = "AN6" ;
NET "lreseto_l" LOC = "AP4" ;
NET "lreadyi_l" LOC = "AN5" ;
NET "ld(31)" LOC = "AF15" ;
NET "ld(30)" LOC = "AF14" ;
NET "ld(29)" LOC = "AL12" ;
NET "ld(28)" LOC = "AL13" ;
NET "ld(27)" LOC = "AJ14" ;
NET "ld(26)" LOC = "AJ13" ;
NET "ld(25)" LOC = "AE15" ;
NET "ld(24)" LOC = "AE14" ;
NET "ld(23)" LOC = "AN11" ;
NET "ld(22)" LOC = "AN12" ;
NET "ld(21)" LOC = "AG12" ;
NET "ld(20)" LOC = "AM11" ;
NET "ld(19)" LOC = "AG14" ;
NET "ld(18)" LOC = "AG13" ;
NET "ld(17)" LOC = "AK11" ;
NET "ld(16)" LOC = "AF13" ;
NET "ld(15)" LOC = "AM7" ;
NET "ld(14)" LOC = "AJ11" ;
NET "ld(13)" LOC = "AP7" ;
NET "ld(12)" LOC = "AM8" ;
NET "ld(11)" LOC = "AN7" ;
NET "ld(10)" LOC = "AH12" ;
NET "ld(9)" LOC = "AN8" ;
NET "ld(8)" LOC = "AM9" ;
NET "ld(7)" LOC = "AP9" ;
NET "ld(6)" LOC = "AL8" ;
NET "ld(5)" LOC = "AL9" ;
NET "ld(4)" LOC = "AL10" ;
NET "ld(3)" LOC = "AJ9" ;
NET "ld(2)" LOC = "AF12" ;
NET "ld(1)" LOC = "AL11" ;
NET "ld(0)" LOC = "AP11" ;
NET "lclk" LOC = "AG18" ;
NET "lbterm_l" LOC = "AP5" ;
NET "lblast_l" LOC = "AP6" ;
NET "lbe_l(3)" LOC = "AG11" ;
NET "lbe_l(2)" LOC = "AP12" ;
NET "lbe_l(1)" LOC = "AN4" ;
NET "lbe_l(0)" LOC = "AN3" ;
NET "lads_l" LOC = "AM6" ;
NET "la(23)" LOC = "AJ18" ;
NET "la(2)" LOC = "AG15" ;
NET "fholda" LOC = "AE12" ;