Re: [partial-reconfig] Simple Question on Opb_ddr Clocking

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Peter,

mlee@ee.ryerson.ca wrote:

> My partial reconfiguration Microblaze design can only run at around 43MHz.
> I am trying get DDR to work with the design, and my DDR has a minimum
> clock limitation of 66MHz. I am using Memec MB2V1000 with Virtex-II. I am
> wondering if it's possible to get this DDR to work with my design? Or both
> DDR Clock and opb_bus (Microblaze) have to run at the same speed (using
> the same clock)?

This is a good question.  It is my understanding that the DDR clock must 
match the OPB clock.  If 66MHz truly is a hard minimum frequency for the 
DDR devices then this could be troublesome.

It would be worth posting your question to the comp.arch.fpga newsgroup, 
and also the microblaze-uclinux list.  It's not uclinux-specific but 
many people there have used this board, and might be able to help.

Regards,

John

___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/