Re: [partial-reconfig] Single Slot Project - Error in assembly phase

[mlee@xxxxxxxxxxxxx]

Hi,

I had similar problems before, too. I just simply unroute those signals
before doing the final assembly.

FPGA Editor script:
----------------------------------------------
select net "GLOBAL_LOGIC*"
unroute
select comp "PWR_VCC_*"
unplace
----------------------------------------------

Give this a shot.


Peter Lee

> RTR'ers:
>
>   I have built the 2 sides (dynamic and static) of an EDK project that
> includes a PowerPC, the PLB bus, an OPB bus, the PCI bus, DDR memory,
> and a single reconfigurable core that is attached to the OPB bus.  The
> static and dynamic sides can be seen in their respective pictures that
> are attached (taken from fpga_editor).
>
> The problem is when I try to "assemble" the 2 sides I get a FATAL_ERROR
> from Xilinx's GUIDE program saying that signals exist that go through
> mulitple route areas, i.e. the 2 sides have an intersection besides the
> connections made by the bus macros.  The error tells me that the signal's
> name is GLOBAL_LOGIC1 and it is coming from the dynamic side --> this is a
> compiler created signal that is not evident in the VHDL.  Also, one can
> see that in the picture of the static side, it has a few signals (the
> greenish ones) that cross over the site where the dynamic logic should go
> EVEN though the .ucf constraints tell it not to do so.  I believe that
> these are the signals to blame for the error, but I haven't quite yet
> figured out how to get PAR to do it's job and route these signals around
> the constrained area of the dynamic side.  Does anyone have any
> suggestions or ideas?
>
> -Jason


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