[partial-reconfig] Problems with Partial Bitmaps

["Pittman, Richard N" <rnpittman@xxxxxxxxxxxx>]

I am not sure what I can do now.  I have followed the design flow as closely
as I could.  I can create working bit maps of all my configurations but when I
use a partial bit map to reconfigure my fpga the module I reconfigured does
not work correctly.  However if i use a partial bit map to change it back to
the original configuration it starts to work again.  I am using tristate io
pins on my data bus that I use for input and output.  The tristate logic that
governs the read and write on the pins is in the top level module.  When I
view the design in pace I see no pseudologic and when I see the final routing
the only thing that crosses the boundary is the clk buffer and the bus wires
associated with the output of the bus macros.  I don't recieve any errors in
the design flow other than the unrouted net errors I would expect.  I would
really appreciate any help that can be provided.  I am about at my wits end.

Neil

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