Re: [partial-reconfig] Question on DPR tutorial by Gregory Mermoud

[yilu@xxxxxxxxxxxxxx]

Hi,

When you synthersize you design in ISE, right-click the systhersize and choose
properties. In the systhesis tag, you can find the "Bus Delimiter", try to
choose others matching your bus-macro.

cheers,

luyi


Quoting Ye Zijia <yezijia@nus.edu.sg>:

> Hi,
>
>      thanks for your reply Peter. Another question i have is if i am using
> Virtex II Pro instead of Spartan 2. What should i change or modify from the
> original design files ? I tried using the bus macro file ,bm_4b_v2p.nmc and
> changing the bm8.vhd files bus1 and bus2 to bm_4b_v2p.nmc from bm_4b_s2.nmc
> but this is the error i get using ngdbuild.
>
> ERROR:NgdBuild:76 - File
> "C:\DPR\implementation\top_level_initial/bm_4b_v2p.nmc"
>
>    cannot be merged into block "busIncToReg_bus2" (TYPE="bm_4b_v2p") because
> one
>
>    or more pins on the block, including pin "LI<3>", were not found in the
> file.
>
>     Please make sure that all pins on the instantiated component match pins
> in
>    the lower-level design block (irrespective of case).  If there are bussed
>    pins on this block, make sure that the upper-level and lower-level
> netlists
>    use the same bus-naming convention.
>
> Can anyone tell me whats went wrong and what i should do to rectify it ?
> Please advise.
>
> Thanks for your time !
>
> Regards,
>
> Zijia
>
>
>
> >Hi,
>
> >They are meant for each different device family.
> >s2 is for Spartan2, v2 is for VirtexII, v2p is VirtexII Pro, etc. etc.
>
> >Regards,
>
> >
> >Peter Lee
>
> > Hi,
> >
> >      thanks for your reply but i have another question. For example
> > under the paran_delimiter there are 6 different *.nmc files. What are
> > the difference between them ?
> >
> > The file names are :
> >
> > 1.bm_4b_s2.nmc
> >
> > 2.bm_4b_s2e.nmc
> >
> > 3.bm_4b_v2.nmc
> >
> > 4.bm_4b_v2p.nmc
> >
> > 5.bm_4b_v.nmc
> >
> > 6.bm_4b_ve.nmc
> >
> > so for the DPR tutorial i should use 1. bm_4b_s2.nmc right ? Thanks
> > for your time and advice !
> >
> > Regards,
> >
> > Zijia
> >
> > On 7/29/05, Ye Zijia <yezijia@nus.edu.sg> wrote:
> >
> >> Hi all,
> >
> >>
> >
> >> I am a total newbie to partial reconfiguration. I am currently trying
> >
> >> out the tutorial on DRP and have this question. I am using XST to
> >
> >> synthesis the design.
> >
> >>
> >
> >> 1. As in the tutorial, the module bm8 should not be declared as a
> >
> >> black box so its source should be in /top directory but what about
> >> the
> >
> >> components of bm8, bm_4b_s2 ? Should it be a black box or where
> >> should
> >
> >> i place the files for Xilinx bus macros ?
> >
> > This is a black box in the sense that you do not provide VHDL code for
> > it, instead you put a file called bm_4b_s2.nmc... but you need it only
> > during the implementation stage. Before that step, this is a black
> > box.
> >
> >> 2. And for Xilinx bus macro files i have angel_delimiter,
> >
> >> paran_delimiter and square_delimiter so which one should be used for
> >
> >> this tutorial ? And there are a few *.nmc files each under each
> >
> >> delimiter, what's the different between the files ?
> >
> > I dont exactly remember, but I think it is paran_delimiter : ( )
> >
> > Anyway, you can simply try each of them... or have a look to the
> > delimiters in the .nmc file by opening it with FPGA editor or
> > translating it in a .xdl file. (ncd2xdl will help you more than once
> > in your project).
> >
> > --
> >
> > Grégory Mermoud <gregory.mermoud@epfl.ch>
> >
> > Master student in Computer Science
> >
> > School of Computer and Communication Sciences
> >
> > Swiss Federal Institute of Technology - Lausanne (EPFL)
> > <http://ic2.epfl.ch/~gmermoud <http://ic2.epfl.ch/~gmermoud> >
> >
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