RE: [partial-reconfig] Problem with partial bitstream

["Javier" <jcastillo@xxxxxxxxxxxxx>]

I will talk about my experience with ISE tools and partial reconf. Before
7.1SP2, my designs only work with 6.3SP3. Since 7.1SP2 the same designs
works fine, I only had to change the DCM connections. 
The design I am using takes the 80% of a XC2V3000, separated in a fixed and
a reconfigurable part which takes each one the 50% of the FPGA area.
My conclusion is that 7.1SP3 works fine with partial reconf. I have tested
my old examples and working over new ones successfully, so I think the tools
haven't got errors. 

Regards

Javier Castillo


-----Mensaje original-----
De: owner-partial-reconfig@itee.uq.edu.au
[mailto:owner-partial-reconfig@itee.uq.edu.au] En nombre de David Kramer
Enviado el: jueves, 04 de agosto de 2005 12:30
Para: partial-reconfig@itee.uq.edu.au
Asunto: Re: [partial-reconfig] Problem with partial bitstream

Hi again,

can someone explain me now, why it works with 6.3i but not with 6.3.03i?
As you said, reinstalling the ISE and not updating it to SP 3 solved the 
problem. Now it works as it should.

>But my earlier question still remains. Can anyone tell me
>how you are mapping the pins for ml310 board which has more
>inputs than clock and more outputs than leds?
>
>This will help me out on designs with more than clocks and leds
>as my ports. I am really stuck on this now.
>  
>
Sorry, I can't help you with that. I'm only using pin B15 as clk_input 
and the eight pins which drives the leds.
Do you know the ML310 User Guide? 
http://www.xilinx.com/products/boards/ml310/current/pcb/sch/ug068.pdf
Maybe this can help you.

Best regards,
David


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