RE: [partial-reconfig] MapLib error with inout signals

[<jcastillo@xxxxxxxxxxxxx>]

Hello, 

  I had the same problem when the RAM controller was inside a module.
The way I solved the problem was very easy, I converted the bidir port
into two and added a port with the control signal of the bidir port. I
put the bidir just in the top level, adding also the logic that controls
the port something like:

assign data=control?data_i:data_o;

It works perfect with the modular flow.

Regards

Javier Castillo
javier.castillo@urjc.es
Universidad Rey Juan Carlos
Madrid
SPAIN


-----Mensaje original-----
De: owner-partial-reconfig@itee.uq.edu.au
[mailto:owner-partial-reconfig@itee.uq.edu.au] En nombre de j-p delahaye
Enviado el: viernes, 12 de agosto de 2005 17:17
Para: partial-reconfig@itee.uq.edu.au
Asunto: [partial-reconfig] MapLib error with inout signals

Hi,
First I want to know how to subscribe to this list, I am also
interesting in partial reconfiguration!

Second, I design application on a Virtex -II device and I have a map
error the same as in the following message:
http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2005/05/msg00007.html
How finally you solve this error Devadutt , I've try a lot of options
but the error is still there:
ERROR:MapLib:492 - Create a dummy tbuf in the context connected to
signal IBAST_OBUF with a location constraint to a single site.
I have this error (happens in the active phase of a fixed module
implementation) on every bidirectionnal signals that go from a fixed
module to the top (IOB pads).

Please heeeeeeelp,

Best,

Jean-Philippe

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