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Re: [partial-reconfig] Reg custom busmacros.
Hello Yilu,
Sorry I made a mistake yesterday. I was using old macro files
instead of the 1bit custom bus macro files. Hence the problem.
Once I found this and rerun the procedure with the correct macro file,
I have things working as expected.
Thanks for your guidance.
Cheers!
LN
On Sat, 13 Aug 2005 yilu@itee.uq.edu.au wrote:
> Hi, LN,
>
> remove the "AREA_GROUP "AG_busmacro1" RANGE = SLICE_X36Y4:SLICE_X36Y4,
> TBUF_X36Y4:TBUF_X36Y4;" from your ucf file, see if it helps.
>
> Cheers,
> yilu
>
> Quoting "Lakshmi Narasimhan. S" <sulakshm@student.utdallas.edu>:
>
> > Hello Yilu,
> > Thanks for your reply. It was quite helpful in me starting
> > with a design.
> >
> > But when I start using the busmacro, I hit the following error
> > during mapping phase.
> >
> > ERROR: Map: 82 - Error while processing the constraint attached to
> > area group "AG_busmacro1". The constraint value equals
> > SLICE_X36Y4:SLICE_X36Y4. The range defined by columns 36,36 and rows
> > 4,4 does not fall on CLB boundary. The internal configuration of the
> > CLB in the given device is different with the FPGA editor or
> > Floorplanner view. Please modify the constraint to fall on CLB
> > boundary.
> >
> >
> > Now I suspect the above error to be because of my TBUF placement
> > in busmacro. Do you think there is some rules to be
> > followed while designing the busmacro placement? is the width
> > between 2 tbufs an issue?
> >
> > I am providing below snippets from busmacro and ucf constraint file.
> >
> > -- snip from custom 1 bit bus macro --
> > inst "TBUF1" "TBUF" , placed R39C24 TBUF_X46Y82 ,
> > cfg "TINV::T IINV::I _SUPERBEL::TRUE"
> > ;
> > inst "TBUF0" "TBUF" , placed R39C23 TBUF_X44Y82 ,
> > cfg "TINV::T IINV::I _SUPERBEL::TRUE"
> > ;
> > net "TBUF_OUT" ,
> > cfg "_NET_PROP::IS_BUS_MACRO:",
> > outpin "TBUF1" O ,
> > outpin "TBUF0" O ,
> > pip R39C23 TOUT0 -> TBUF2 ,
> > pip R39C24 TOUT1 -> TBUF3 ,
> > # net "TBUF_OUT" loads=0 drivers=2 pips=2 rtpips=0
> > ;
> >
> > ----
> >
> >
> > -- snip from toplevel.ucf file for this project --
> > AREA_GROUP "AG_busmacro1" RANGE = SLICE_X36Y4:SLICE_X36Y4,
> > TBUF_X36Y4:TBUF_X36Y4;
> >
> > INST "busmacro1" LOC = "TBUF_X36Y4";
> > INST "busmacro1" AREA_GROUP = "AG_busmacro1" ;
> > ---- snip end ---
> >
> >
> > Can anyone provide some inputs on how to solve this issue.
> >
> > Thanks
> > LN
> >
> >
> >
> >
> > On Fri, 12 Aug 2005 yilu@itee.uq.edu.au wrote:
> >
> > > Hi, LN
> > >
> > > You can build the TBUF based busmacro directly by fpga_editor.
> > >
> > > Firstly, adding the TBUFs as components. (choose the TBUF and click
> > "EDIT->ADD")
> > >
> > > Then, route you bus macro. click ( with Ctrl) a TBUF -> short line -> long
> > line
> > > -> short line -> another TBUF (click "TOOLS->route->manuly route"). and
> > your
> > > busmacro will be here now. Remerber to show the connector when you build
> > you
> > > bus macro, that can make sure you choose right short line which connect the
> > > TBUF and long line.
> > >
> > > Last, use "xdl -ncd2xdl yourmacro.ncm" to create a xdl file add cfg
> > "_NET_PROP::
> > > IS_BUS_MACRO:" to your busmacro. you can see the the difference between
> > your
> > > busmacro and xilinx busmacro. use "xdl -xdl2ncd yourmacro.xdl". then you
> > can
> > > use your busmacro.
> > >
> > > My busmacro built in this way works.
> > >
> > > hope it helpful.
> > >
> > > cheers,
> > > yilu
> > >
> > >
> > >
> > > Quoting "Lakshmi Narasimhan. S" <sulakshm@student.utdallas.edu>:
> > >
> > >
> > >
> > > > Hello Team,
> > > > I am looking at creating custom busmacros.
> > > >
> > > > I have been going through Throvingers thesis and XDL design language,
> > > > but there are a lot many things that havent sinked in yet.
> > > >
> > > > I remember seeing in this alias, a simple 1 bit Bus Macro
> > > > designed by someone. I would like to start with that, but
> > > > I am not able to figure out that thread..
> > > > (BTW How do I search in this mail group, I do not find any option)
> > > >
> > > > Can anyone share me with that design?
> > > >
> > > > 1) Is XDL definition the only way to create custom busmacros?
> > > > 2) Can FPGA editors be used directly? Where can I read more about it.
> > > > 3) And are bus macro placement restricted by TBUF primitive placement
> > > > on the board? I guess TBUf have fixed placement, correct?
> > > >
> > > > Can anyone shed more light on the design of custom busmacros?
> > > > Any documents reference designs will be helpful.
> > > >
> > > >
> > > > Thanks
> > > > LN
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