Re: [partial-reconfig] Partially Reconfigurable ML310 Design

["Lakshmi Narasimhan. S" <sulakshm@xxxxxxxxxxxxxxxxxxxx>]

Hello Jason,

I am using ML310 and my objective is to do dynamic reconfiguration
through a microprocessor acting as a controller. Currently I am
stuck with building a processor + kernel, that leaves much real estate
for performing dynamic reconfiguration.
I am trying PPC + montavista linux, microblaze + uclinux. I have had
some success with PPC + montavista, but havent successfully come up
with uclinux because of issues with the FLASH onboard ML310.
Hope someone helps me out here. I have seen in this very group that
John had a working design that does the very same thing. I am not
sure which board he used, nor which version of xilinx tools he had
used. Maybe he will answer here with more info. But I have
come to realize that making things work with one board doesnt make
things easy for someone working with a different board. ML310 has
been one of those not making life easier atleast for Dyn Reconfig.

On the demonstration part, I have had success but for trivial designs
like the blinking leds and DPR tutorials. Nothing better yet.
I hit a lots of issues with this simple design to get the right
tools. Since you mention tools, I had mine working only with 6.3 with
no service package update. Others failed.

I sincerely would like to have a pool of inputs here from people
working mainly on ML310 board. Please contribute your progress, issues
and workarounds you had used. That would be highly helpful to
everyone.

Thanks!
LN

On Tue, 16 Aug 2005 jagron@ittc.ku.edu wrote:

> PR Board:
>
>   I have been working on a dynamically reconfigurable design for the ML310
> that allows dynamic reconfiguration of OPB cores using the on-chip
> PowerPC processors.  I have been working on this for over 8 months and
> have used the 6.2, 6.3, and 7.1 tools with and without all of the
> service packs with absolutely no luck.  No matter what the configuration
> of the system, I will get assembly errors (usually DRC related) in
> either the MAP or PAR stages that result from pieces of Xilinx's code
> (i.e. PCI, DDR, PLB, or OPB components).  I have opened up 2 webcases
> with Xilinx and both have taken them about 3 months for them to finally
> tell me that it is a bug in their tools, and no workaround exists (the
> fix may or may not appear in future releases of the tools).  Does this
> mean that the modular design flow for partial reconfiguration with a
> full-on PowerPC thrown in the mix is impossible?  What resources do we
> have as "partial reconfigurators" if Xilinx themselves does not offer
> any help as to why their tools do not function as advertised?  If
> partial reconfiguration is this hard and arduous to do, and still you
> don't get the results that are suggested, is it still worth it to pursue
> (I don't know the answer to this question yet)?
>
> I have created some supplemental documentation that goes along with
> XAPP290 and Gregory Mermoud's tutorial at
> http://wiki.ittc.ku.edu/rtrjvm/EDK_and_MD that helps to explain how to
> implement the modular design flow for partial reconfiguration within EDK
> and I have posted the project that I've been working on at
> http://www.ittc.ku.edu/project7.tar.gz.  I've created this to try to fill
> in some of the knowledge gaps that I have noticed in the documentation
> that is available, but I have yet to get my design fully working (both the
> static and dynamic "sides" of my design can be built, but I have never
> been able to fully assemble them).
>
> I wish everyone working on this stuff good luck, but at the same time, if
> Xilinx isn't willing to deal with making partial reconfiguration
> commericially useable, then I'm not sure if I want to continue to bang my
> head against the wall in order to make a partially reconfigurable design
> that can blink lights in different orders or add AND subtract.... I think
> I will just buy a bigger and more efficient FPGA.  But, in conclusion,
> have any of you ever seen a working design on a Virtex-II Pro that wasn't
> trivial?
>
> Sorry, just needed to vent a little bit,
> - Jason Agron, jagron@ittc.ku.edu,
>   ITTC - Information & Telecommunication Technology Center,
>   University of Kansas
>
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