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AW: [partial-reconfig] Partial Reconfiguration Area Constraints
Hallo Waltraud,
Korrektur liegt auf Deinem
Schreibtisch.
Danke für die Mühe!
Klaus
Hello all,
It has been mentioned in the Xilinx partial
reconfiguration app note that one must "physically" open the design in FPGA
Editor and observe the design to make sure the routing is within the specified
area. I have experimented with several designs using the Xilinx modular
design flow and have observed that whenever a designs' area constraints are
not met the Placer and route tool reports an error. I would like to know
if one can completely depend on the Place and Route tools report to decide if
the area constraint is not met (for routing and logic) or one should always
resort to manual observation.
Thanks
Harish