Re: [partial-reconfig] Partial Reconfiguration Area Constraints

[Ron Sass <rsass@xxxxxxxxxxx>]

Javier, Gregory, Harish--

I have been curious about the damage one could cause too.  Xilinx
has had ominous warnings about bad bitstreams for a long time (I
remember seeing warnings about 4000-series parts).  With Virtex-II
and Virtex-II Pro parts, the reconfiguration is supposed to be "glitch-less"
in that if the old and the new configuration bit is the same, then
the output signals dependent on that configuration bit should not
temporarily bounce.  So based on that, here's what I am guessing:

<speculation>
I am guessing that problem is going to be current-related.  If you
have a (logical) column of CLBs that are connected to routing network
through a connection boxes and routing boxes, then there are several
ways of configuring multiple CLBs to drive the same vertical route.

So my guess is (and this is very sketchy because I don't know enough
of CMOS implementation and I may be naively describing a TTL problem)
that if multiple CLBs are trying to drive that routing resource,
you create a situation where one is providing a path to ground whereas
the another is trying to raise the voltage to VDD.  The one trying
to raise the voltage, will drive as much current as it can over a
near-zero resistance path.  High current raises the temperature at
the transisitor and the heat physically damages that die.

Now I imagine that one transistor is not going to be able to drive
enough current to create enough heat to do any real damage, so I'm
guessing you'd have to have several transistors trying to raise the
line to VDD (and maybe parallel low-resistance paths to ground?).
Moreover, the damage won't be instantaneous since it will take a
certain amount of time for the device to heat up (10s to 1000s of
ms???).

If this is the case, then Xilinx's fear would be that during partial
reconfiguration, you are changing the routes to the routing network
for a logical column of CLBs *one frame at a time*.  So If you configure
some of the top frames and then for any number of reasons there is
*a delay* before you configure frames at the bottom of the column, then
you could create a situation where there is enough time to increase
the temperature around that 'hot' path to cause damage.
</speculation>

Any comments, clarifications, debunking of my little theory? :-)

Honestly, I am speculating based on outside information -- like why
do we need bus macros etc.  And admittedly I don't know how Xilinx
actually implements their routing, which would make a huge difference.

A small nihilistic part of me wants to construct this dangerous
situation and see what happens.  But like, Javier, who has FPGAs
to lose!

Ron


> Hello Grégory,
> 
>   I have read many times that an incorrect routing can damage the FPGA, also
> I eared that a wrong encrypted bitstream could also damage it. But I don’t
> know anybody that has damage one. Since the bitstream has CRC mechanism it
> not possible to send a bad encrypted one to the FPGA. I am working with the
> ICAP and until I wrote the ICAP controller successfully (bits inverted) I
> sent wrong bitstreams to the FPGA and because of the CRC it just ignores
> them. I also don’t understand how a wrong routing can destroy the logic, I
> can imagine some cases but they are very tricky. Obviously I am not going to
> try to destroy one FPGA to ascertain if it could be done, but I am
> interested on it and I want to know if they are legends or really a FPGA
> could be damage with a bitstream.
> 
> Regards
> 
> Javier Castillo
> Universidad Rey Juan Carlos
> Madrid (SPAIN)
> javier.castillo@urjc.es
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