Re: [partial-reconfig] Partial Reconfiguration Area Constraints

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Ron Sass wrote:

> Honestly, I am speculating based on outside information -- like why
> do we need bus macros etc.  And admittedly I don't know how Xilinx
> actually implements their routing, which would make a huge difference.
> 
> A small nihilistic part of me wants to construct this dangerous
> situation and see what happens.  But like, Javier, who has FPGAs
> to lose!

Whenever I talk to people, both Xilinx and non-Xilinx, about this, the
consistent message I get is that you really need to work at it to cause
physical damage.

One experiment I heard about was the idea of burning unique patterns
into the FPGA as a kind of security mechanism. Deliberately cook certain
CLBs or routes, then you could tie a particular bitstream to a specific
FPGA device, burned with that key.  An interesting idea, but the main
point was that it was very, very difficult to actually cause physical
damage, even when you are trying.

So, I wouldn't try it with a V4-60LX, but an S3-200?  You bet!

Cheers,

John



___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/