[partial-reconfig] Spartan-IIE Module Boundary doubt...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hello everyone...

Signing in after a long time... I hope you're all doing fine...

I have this one little doubt about area constraints on Spartan-IIE
devices... unlike the Virtex-II, it seems the Spartan-IIE allows module
boundaries to fall virtually anywhere, as long as its on a column
boundary... 

A look at the Spartan-IIE, courtesy FPGA_Editor, Floorplanner or PACE,
shows that it is arranged in Rows and Columns, with each CLB made up of
two slices... If the four slice rule is to be followed, placing module
boundaries at places where the slices in the module taken horizontally
do not add up to a multiple of four, should not work... But it does...

Another interesting feature of the Spartan-IIE is that the Rows and
Columns are numbered from 1 onwards, instead of 0... So if we begin at
the first column (numbered 1), the right-side boundary of the first
module should only be allowed to fall *after* columns 2, 4, 6, 8
onwards, since this way the slices would add up to 4, 8, 12, 16
respectively... however, placing the boundary anywhere else seems to
work just fine...

In the Gregory Mermoud tutorial (which by the way is fast becoming a
standard text in the DPR world), the module boundary falls after column
19... (in other words, on column 20)... the slices add up to 38,
horizontally, which is not a multiple of 4, yet the design works fine... 

Maybe I'm missing something here... could it be that the 0th column,
which doesn't really exist, needs to be taken into account nonetheless?
This would add up to 40 slices, which conforms to the four slice rule... 

I'll appreciate some comments on this... 

:)

Sincerely,
Umar

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