[partial-reconfig] Spartan-IIE Custom BMs...

[vutukuhc@xxxxxxxxxxxx]

Hello Umar,

I have developed a similar bus macro for Virtex device using only 2 CLB's on
each side of the module. I am still developing some additional modules and have
not tested it. Jens Thorvinger's thesis was real helpful to me in that effort.

I am experiencing some issues with the Active Module implementation phase. The
PAR fails with an error message that one net is unrouted, but in the par report
no information is provided with regard to which net is not routed. Upon opening
the design in FPGA Editor and looking for unrouted nets I found that the list
of the nets shown were for the top level design. I have several of the designs
and each of them comes up with the same error at the end. Did any of you face a
similar issue? Is there any other way I can verify the design other than by
simulating the placed and routed design?

Thanks
Harish

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