Re: [partial-reconfig] Spartan-IIE Custom BMs...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hi Harish...

About the Virtex-II BMs... don't the original Virtex-II BMs use two CLBs
on either side too? Could you upload your BMs so we can see the
difference? I'll appreciate that... I agree about Jens Thorvinger's
thesis... I'm about to begin writing my own thesis and it'll probably
have several references to Jens' thesis...

About the problem you're facing with PAR... if the unrouted nets are
from the top level, could it be that there's some connection you messed
up in the top-level files? In that case it might well be a minor
error... checking the synthesis report would help... if it doesn't work,
try increasing the size of the modules, or using a different FPGA...
maybe its to do with the amount of logic in a module...

PAR for RTR designs is a hit and miss thing... I've discovered that
keeping the design as neat as possible helps... doing away with any
loadless nets for instance... often, making completely unrelated changes
to the design causes it to route properly... just yesterday I had posted
about a weird PAR error for which I could find nothing online... there
was one module that appeared to be causing all the trouble... all I did
was type it out again differently... the synthesis results were exactly
the same, as was the RTL Schematic... yet PAR completed this time... 

:)

Sincerely,
Umar

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