Re: [partial-reconfig] Spartan-IIE Custom BMs...

[vutukuhc@xxxxxxxxxxxx]

Hello Umar,

Check the following Answer record from Xilinx regarding the same. I think you
might be experiencing the same issue(17204)
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17204http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17204

Lakshmi -- You mentioned that you always have some unrouted nets in 
your design
during active module implementation phase. Could you also confirm if you had
any issues with the partial bitstrem that you generated.

Thanks
Harish
Quoting "Lakshmi Narasimhan. S" <sulakshm@student.utdallas.edu>:

>
>
>
> On Thu, 25 Aug 2005 vutukuhc@ececs.uc.edu wrote:
>
>> Hello Umar,
>>
>> I have developed a similar bus macro for Virtex device using only 2 CLB's on
>> each side of the module. I am still developing some additional 
>> modules and have
>> not tested it. Jens Thorvinger's thesis was real helpful to me in 
>> that effort.
>>
>> I am experiencing some issues with the Active Module implementation 
>> phase. The
>> PAR fails with an error message that one net is unrouted, but in the 
>> par report
>> no information is provided with regard to which net is not routed. 
>> Upon opening
>> the design in FPGA Editor and looking for unrouted nets I found that 
>> the list
>
> Hello Harish,
>
> Actually it is okay to have unrouted nets with the active module
> phase, as long as final assemble module is able to place and route
> successfully.
>
> It works, I always have some unrouted nets after my routing phase.
>
> Hope this helps.
>
> Thanks
> LN
>
>
>
>> of the nets shown were for the top level design. I have several of 
>> the designs
>> and each of them comes up with the same error at the end. Did any of 
>> you face a
>> similar issue? Is there any other way I can verify the design other than by
>> simulating the placed and routed design?
>>
>> Thanks
>> Harish
>>
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