[partial-reconfig] DCM in DPR.

["Lakshmi Narasimhan. S" <sulakshm@xxxxxxxxxxxxxxxxxxxx>]

Hello team,
I had to use a DCM to clock my design at 66Mhz because the timing
constraint was not met for 100 Mhz. I use ML310 board.

The system has a microblaze microprocessor on one side and
reconfig module on the other.

I am facing problems connecting the CLK0 and CLKFB ports
on DCM.

From the manuals I read that CLK0 is an output port which
has to be fed back to CLKFB through a BUFG or IOB for
phase synchronization.

I had used BUFG, BUFGMUX, IOBUF and just BUF. All of them
fail at the assemble stage with various errors and it doesnt
work.

Can you let me know how to connect these ports what buffers
to use?

I have instantiated DCM in toplevel module.

Thanks
LN



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