[partial-reconfig] Another BM Question...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hi...

Just noticed something in xapp290 that I hadn't noticed earlier...

In Appendix C, it says...

"5. If the bus macro is in the leftmost position, bits 2 and 3 cannot go
left-to-right.
6. If the bus macro is in the rightmost position, bits 0 and 1 cannot go
right-to-left."

I can't seem to understand what this means or implies... does it mean
that if two modules A and B are communicating using a BM and A lies at
the left edge of the FPGA, it cannot send bits 2 and 3 to B if the BM
falls on x=0? If so, why?

Needless to say, a design revision looms threatningly on the horizon if
this is so... :( ...

Sincerely,
Umar

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