Re: [partial-reconfig] Another BM Question...

[<bartosr@xxxxxxxxxx>]

Hi Umar,

I think that these notes are incorrect. Unreachable directions are opposite.
In the leftmost position it should be right-to-left and in the rightmost position
it should be left-to-right.
Why ? Because the BM provided by Xilinx uses all 4 long lines in a one row
and output from each long line is in separated column (output from long line
is connected to switch matrix). So four long lines need four columns (eight X position
of slices). But in the leftmost position of BM (in the rightmost position too, of course)
you have only two columns (four X positions of slices and tri-state buffers too).
So you can't interconnect long line with another logic.

Sincerely,
Roman Bartosinski

______________________________________________________________
> Od: misfit_05@fastmail.fm
> Komu: partial-reconfig@itee.uq.edu.au
> CC: 
> Datum: 03.10.2005 08:55
> Předmět: [partial-reconfig] Another BM Question...
>
> Hi...
> 
> Just noticed something in xapp290 that I hadn't noticed earlier...
> 
> In Appendix C, it says...
> 
> "5. If the bus macro is in the leftmost position, bits 2 and 3 cannot go
> left-to-right.
> 6. If the bus macro is in the rightmost position, bits 0 and 1 cannot go
> right-to-left."
> 
> I can't seem to understand what this means or implies... does it mean
> that if two modules A and B are communicating using a BM and A lies at
> the left edge of the FPGA, it cannot send bits 2 and 3 to B if the BM
> falls on x=0? If so, why?
> 
> Needless to say, a design revision looms threatningly on the horizon if
> this is so... :( ...
> 
> Sincerely,
> Umar
> 
> -- 
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