Roman, John... Thank you very much, both of you, for your replies... It turns out that in correcting an error, the Xilinx guys made another... the previous version of xapp290 said for a left-most BM, bits 0 and 1 cannot go right-to-left... someone asked if this was correct, and they replied that it wasn't, and that bits 2 and 3 cannot move right-to-left... In the "corrected" version though, they fixed the bits but messed up the direction... The use of one output per CLB column (i.e. two horizontal slices) remains a somewhat contentious issue, though... in August I had posted about using two CLB columns (four horizontal slices) for a Spartan-IIE BM, similar to the Virtex-II BM... http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2005/08/msg00054.html Apart from one reply, by Harish, who said he had built a similar BM for the Virtex family, there weren't any others... I had therefore gone ahead with the technique, building several BMs that I used for some designs... none of them have made it to an FPGA yet, but the design flow went ahead with no problems whatsoever, with the final PAR routing the design perfectly with no errors... However, Roman's post, and a look at the Spartan-IIE datasheets raised several doubts in my mind about whether such BMs would actually work... the datasheet provides a figure which seems to vindicate Roman about one BM output being accessed by one CLB... using FPGA_Editor also seems to suggest that the output from a single line goes to a CLB GRM, and therefore four CLBs will be needed to read four lines... I'm uploading the figure... A close look in FPGA_Editor at my designs, however, suggests that all is well... all bits are apparently read at the destination module, although some lines continue all the way to the edge of the device and travel down vertically along the edge on to the CLBs that need them... the outputs to the GRM don't really come into play... In the design I speak of, the BMs are all placed on the left-most position... some move left-to-right and therefore should work... I can fix the others by using the technique John suggests, but if the two-CLB theory fails, my design, which is the way it is for maximum module density, would fall flat on its face... I can unpload the final .ncd file if anyone would like to have a look at it... Thanks in advance... really worried here... :) Sincerely, Umar -- http://www.fastmail.fm - A fast, anti-spam email service.
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