Re: [partial-reconfig] Another BM Question...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hello everyone...

A little update on the problems for which I wanted help on...

I spent the last day or so poring over the .ncd files in FPGA_Editor,
trying to come up with some answers... in the light of my previous posts
regarding the four-column Bus Macro thing and the unreadable bits with
BMs on left-most and right-most locations, the following came to light:

1) It appears that sending data using the Custom BM I had uploaded in
August is very much possible... I had suggested using two columns only
for the BMs, utilizing all four TBUFs... a look at the figure from the
Spartan-IIE datasheet I had uploaded last week also confirms that two
bits can be written from one column... however, for reading from this
BM, four columns are indeed necessary, since only one bit is read every
column... as Roman had said in his post last week, that one bit goes to
the switch matrix associated with the CLB in that column falling on the
relevant row... 

2) However, if the recieving module lies on the left or right edge of
the FPGA, the routed .ncd files suggest that all bits not read in this
manner are nevertheless routed... they go all the way to the edge of the
FPGA, and then move vertically upwards or downwards to what appear to be
switch matrices lying along the edges... these switch matrices also
appear to be used for sending I/O's on to their destinations... 

3) Modules not lying on the edges do not however route the signals in
this manner, and four columns are required... if four columns are not
used, PAR either results in an unrouted design, or, in one case I
observed, succeeds and reports no unrouted signals, but closer scrutiny
reveals that the bits that haven't been read by the columns and sent to
the switch matrices are in fact missing altogether, with the inputs in
the transmitting module unconnected to the TBUFs involved...

All this has greatly helped my understanding of the situation, and, from
ruing the fact that my design techniques were based on flimsy logic, I
am now grateful that I can now correct them... the only doubts that
remain are about the BMs in left-most and right-most positions not
accepting certain bits... I would greatly appreciate help on this
issue...

My understanding was that BMs in left-most positions were ones that
featured TBUFs in columns 0, 1, 2 and 3 (or in case of the various
Spartan families, columns 1, 2, 3 and 4, given the missing 0th
column)... with each column featuring the switch matrix and a 1-bit 
output going to this matrix, shouldn't it be possible to read and write
all bits? I believe I have failed to understand what is meant by
left-most and right-most positions... maybe this BM, featuring TBUFs
from the first four columns, doesn't qualify as having been placed on
the left-most location?

I hope someone can chime in with some help in this regard... thank you
all for bearing with some really long posts...

:)

Sincerely,
Umar

-- 
http://www.fastmail.fm - And now for something completely different…


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