[partial-reconfig] Re: [microblaze-uclinux] sram failure

["Lakshmi Narasimhan. S" <sulakshm@xxxxxxxxxxxxxxxxxxxx>]

[I am cross posting two groups.. since I feel its related]

Hello Eric,
I have the same issue. But its with Dynamic Partial Reconfiguration
flow. I see no errors with placement, routing and timing. But
still the design fails when put on board, it just hangs waiting for
response from the DDR.
> Starting MemoryTest for DDR_SDRAM_1:
>    Running 32-bit test...

With a regular EDK build I do not see this issue.

I am using ML310 Virtex II pro board.

Has anyone build and tested successfully a design with DDRAM on
ML310 using partial reconfig flow. The xapp290 also mentions
to avoid using DCM. But I see that DDRAM uses DCM. Is that
a reason? Any ideas team?

Thanks
LN


On Mon, 17 Oct 2005, John Williams wrote:

> Eric Lynum wrote:
> >
> > I've switched over to a v2 pro eval board with 64M of sdram and now I'm
> > failing my memory test.  All it does is just say
> > Starting MemoryTest for DDR_SDRAM_1:
> >   Running 32-bit test...
> >
> > +t just hangs at that point.  I'm looking at bad SRAM or something else that
> > is missing.
>
> Exactly which board are you using?
>
> What steps did you use to create the hardware system (roll-your-own, or
> Base System Builder, or ...)?
>
> John
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@itee.uq.edu.au
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
___________________________
partial-reconfig mailing list
partial-reconfig@itee.uq.edu.au
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/