[partial-reconfig] VersaRing and Spartan-IIE Routing...

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

Hello all...

Kept waiting for replies to my previous questions... with none
forthcoming, I worked around most of the problems... my queries now boil
down to the following...

1) Has anyone noticed the VersaRing (or whatever the name is for the
switch matrices along the I/Os) coming into the picture in designs for
Spartan-IIE's? I had earlier mentioned that I had experimented with
modules just two columns wide, trying to make them recieve four bits per
BM... of course, with one bit read out every column, this shouldn't be
possible, and my experiments suggest that it isn't possible for modules
that do not border the edges, and also for Virtex-II modules no matter
where they are, but for the Spartan-IIE, the bits not read out to the
column switch matrices go all the way to the edge of the FPGA to the
switch matrices before the I/Os, and from there are routed to their
destinations using vertical longlines... PAR works perfectly and there
are no missing or unrouted signals... To compare this setup with the
"orthodox" four-column width for reading all four BM outputs, I modified
the module to cover four columns... as expected, bits are read out at
the columns, but even here, some lines continue to the I/O switch
matrices, even when they could have been read at the columns, and in
some cases, even when they have already been read... the module contains
a lot of BRAMs, but even lines not destined for the BRAMs behave in this
manner...

2) This follows from 1) above... if it routes, and routes with nothing
missing, is it destined to work?

Fingers crossed, answers requested...

:)

Sincerely,
Umar

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