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[partial-reconfig] BusMacro Problem



I am a newbie in partial reconfiguration. I am trying to do a partial
reconfigurable design on Virtex-E FPGA. I've tried to adapt the design
in Grégory Mermoud's tutorial to Virtex-E. Tutorial:
http://ic2.epfl.ch/~gmermoud/files/publications/DPRtutorial.pdf

However I have some problems:
In the initial budgeting of module based partial reconfiguration some
warnings occured such as: 

WARNING:PhysSimExpander:5 - TBUF symbol `t4H_<0>':  The following pins
were
   connected on the outside of block "t4H_<0>" but left unconnected
within the
   block:  T
WARNING:PhysSimExpander:5 - TBUF symbol `t3G_<1>':  The following pins
were
   connected on the outside of block "t3G_<1>" but left unconnected
within the
   block:  T
....

These warnings also caused the mapping tool to fail. Then I've
converted the bm_4b_ve.ncd bus macro to xdl file with utility ncd2xdl.

There are some lines in the xdl file such as:

 inst "t4H_<0>" "TBUF" , placed R1C16 TBUF_R1C16.1 ,
   cfg "TMUX::0 IMUX::I _SUPERBEL::TRUE"
   ;
inst "t3G_<1>" "TBUF" , placed R1C15 TBUF_R1C15.0 ,
   cfg "TMUX::0 IMUX::I _SUPERBEL::TRUE"
   ;
........

However in the other FPGA family bus macros  (bm_4b_s2, bm_4b_v2...)
these lines appear as 
 cfg "TMUX::T IMUX::I _SUPERBEL::TRUE"

I've changed all these lines in bm_4b_ve.xdl  as in the other bus
macros(I 've changed TMUX::0 to TMUX::T) then these warnings
disappeared.

However in the active implementation phase PAR gave some errors like:
ERROR:DesignRules:576 - Netcheck: The signal dataL1<4> has a sigpin on
the comp
   busIncToReg_bus2/t4D_<0> that is not in the same route area as
another sigpin
   of the same signal.  This is not permited for Modules in partial
   reconfiguration mode unless the signal has the property
IS_BUS_MACRO.


My two questions are:

1-Is the Virtex-E busmacro (bm_4b_ve.ngc) given by Xilinx is true? (In
other words is there anyone that achieve successful partial
reconfiguration with this busmacro?)
2- How can the error given by PAR can be corrected?

Thank you for your interest
Regards,
Aydin Coskuner



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