Re: [partial-reconfig] BusMacro Problem

["Lakshmi Narasimhan. S" <sulakshm@xxxxxxxxxxxxxxxxxxxx>]

On Tue, 25 Oct 2005, Aydin Coskuner wrote:
<snipped>

> However in the active implementation phase PAR gave some errors like:
> ERROR:DesignRules:576 - Netcheck: The signal dataL1<4> has a sigpin on
> the comp
>    busIncToReg_bus2/t4D_<0> that is not in the same route area as
> another sigpin
>    of the same signal.  This is not permited for Modules in partial
>    reconfiguration mode unless the signal has the property
> IS_BUS_MACRO.
>
>
> My two questions are:
>
> 1-Is the Virtex-E busmacro (bm_4b_ve.ngc) given by Xilinx is true? (In
> other words is there anyone that achieve successful partial
> reconfiguration with this busmacro?)

I cant answer that! I use Virtex II Pro ML310 board.

> 2- How can the error given by PAR can be corrected?

Please note that sometimes you do get these errors during par.
But if you do have a look with FPGA editor you *shouldnt* see
any of those signals crossing module boundaries.
If that is followed then I have seen it generally works well.

See whether this works for you.

Thanks
LN


>
> Thank you for your interest
> Regards,
> Aydin Coskuner
>
>
>
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