[partial-reconfig] Bus macro in VHDL

[javier.castillo@xxxxxxx]

Hello,

   I am trying to develop a bus macro in VHDL based on BUFT for a Virtex2 FPGA.
The first attemp was to do a simple one line macro like the one below.
I have many problems. I can´t include an output port attached to the two outputs
of the tristates because the sinthesizer gives me an error so I connect a line
between the two outputs and try to add the output using fpga_editor.
The line is not routed and when trying to route it the fpga_editor crash.

Has anybody some experience in this topic and can help me?

Regards

Javier Castillo


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity bm_xc2v_2modules is
    Port ( RI: in std_logic;
	  RT: in std_logic;
	  LI: in std_logic;
	  LT: in std_logic
         );
end bm_xc2v_2modules;

architecture macro of bm_xc2v_2modules is

attribute loc : string;
attribute loc of tbuf_1 : label is "TBUF_X62Y126";
attribute loc of tbuf_0 : label is "TBUF_X66Y126";

signal TBUF : std_logic;

begin

tbuf_0 : BUFT port map(I=>LI,O=>TBUF,T=>LT);
tbuf_1 : BUFT port map(I=>RI,O=>TBUF,T=>RT);


end architecture;

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