Re: [partial-reconfig] Bus macro in VHDL

[Thomas Reinemann <Thomas.Reinemann@xxxxxxxxxxxxxxxxxxxxxxxxxx>]

javier.castillo@xxxxxxx schrieb:
> Hi,
> 
>   What I want to do is a bus macro as in the post you link. But instead of
> develop it completely using fpga editor I want to instantiate the components
> and the nets in VHDL to make the process easier.
> At this moment using the code below and fighting with fpga editor I sucessfully
> create a one line bus macro. The idea is to extend to a bus macro similar to
> Jens Thorvinger(I dont know if it is well written :)) one, that means, one
> fixed part and more than one reconfigurable. That is because I want to hear
> experiences from other people designing bus macros with TBUF in VHDL.

We avoid using TBUF based BMs, since you cannot ensure the signal within
 the reconfig area during reconfiguration. Therefore it is better to use
LUT based BMs. Keep in mind, a Virtex4 has not TBUFs.

Bye Tom
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