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Re: [partial-reconfig] Bus macro in VHDL
javier.castillo@xxxxxxx schrieb:
>>We avoid using TBUF based BMs, since you cannot ensure the signal within the
>>reconfig area during reconfiguration. Therefore it is better to use LUT based
>
> BMs. >Keep in mind, a Virtex4 has not TBUFs.
>
>
>>Bye Tom
>
>
> Yes, I am agree. But I have on doubt maybe you can resolve, I have been
> evaluating the possibility of develop the BM for Virtex2 using LUTs, but I dont
> know if it is possible to create a BM that connects a fixed area with two
> reconfigurable areas using LUTs. Think that the data_out bus of the
> reconfigurable areas should be shared and the use of tribufs is perfect for it.
Generally, you can't ensure a signal's state within a reconfigurable
area during reconfig, since its routing may be broken by the reconfig
process. That means, you can't be sure that your tri-state enable input
of the TBUF is high during reconfig and therefore you can't trust this
TBUFs output. To avoid a collision on the long line which belongs to
that TBUF all other TBUFs belonging to this line have to go to 'Z'.
> With LUTs we should implement a multiplexor controled by the strobe lines to
> control multiples reconfigurable areas accesing the same line.
> Even more. The LUTs based macro we've seen and we've develop dont use the long
> lines of the FPGA so they only can connect two adyacent modules.
> In brief for a application with more than one reconfigurable area the BM based
> in LUTs must implement a mux inside it and has to connect to the long lines of
> the FPGA.
> Do you think it could be done?
Yes, we have applied a paper to the RAW 2006, in which we describe such
a system. We use a hard macro which straddles the slots and contains the
multiplexers. The muxers are controlled by the slot's reset and an
output enable of the competing slots, generated by the slots. To avoid
trouble during reconfig the slot's reset is generated within the fixed area.
Bye Tom
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