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RE: [partial-reconfig] Map Error



Dear Ian,
               i tired setting XIL_MAP_NODRC=1 but got the same old error :
 
>            ERROR:MapLib:711 - A Modular Design has been detected.  Map has detected an
>            expanded block Internal_Vcc_Fix that is not a Module with AREA_GROUP AG_fix.
>            This is not a recommended practice.  Please refer to the Modular Design
>            chapter in the Development System Reference Guide for more information.
>        
 
Did i do something wrong ?
 
Regards,
 
Zijia

	-----Original Message----- 
	From: owner-partial-reconfig@xxxxxxxxxxxxxx 代表 Ian Colwill 
	Sent: 20/12/2005 (星期二) PM 8:04 
	To: partial-reconfig@xxxxxxxxxxxxxx 
	Cc: 
	Subject: Re: [partial-reconfig] Map Error
	
	

	If you are using a windows system,at the command prompt type:
	
	set XIL_MAP_NODRC=1
	
	to check the currently set env variables just type 'set'
	
	/Ian
	
	
	
	Ye Zijia wrote:
	
	>Dear Ian,
	>              thanks for your reply. One question i have is how do i set the global variable ? Do i set it at command line or something else?
	>
	>Regards,
	>
	>Zijia
	>
	>       -----Original Message-----
	>       From: owner-partial-reconfig@xxxxxxxxxxxxxx 代表 Ian Colwill
	>       Sent: 19/12/2005 (星期一) PM 9:01
	>       To: partial-reconfig@xxxxxxxxxxxxxx
	>       Cc:
	>       Subject: Re: [partial-reconfig] Map Error
	>      
	>      
	>
	>       I have exactly the problem since moving from ISE 6.3 to 7.1. It appears
	>       that the map program won't allow anything which isn't a module and/or
	>       has conflicting placement constraints with a module to be inluded. Some
	>       new rulecheck for Modular design I guess, looks like they forgot about
	>       PDR. I have opened a webcase with Xilinx, I'll let you know as soon as I
	>       get an answer. Until then it may be possible to deselect these the map
	>       DRC by setting a global variable. try
	>      
	>       set XIL_MAP_NODRC=1
	>      
	>      
	>       /Ian
	>      
	>      
	>      
	>       Ye Zijia wrote:
	>      
	>       >Hi,
	>       >     i am trying the tutorial from http://elektronica.ehb.be/reco/PartialTutorial.htm on ISE 7.1i sp4 but encountered the following error during the active implementation phase.
	>       >
	>       >ERROR:MapLib:711 - A Modular Design has been detected.  Map has detected an
	>       >   expanded block Internal_Vcc_Fix that is not a Module with AREA_GROUP AG_fix.
	>       >   This is not a recommended practice.  Please refer to the Modular Design
	>       >   chapter in the Development System Reference Guide for more information.
	>       >
	>       >Has anyone managed to get this tutorial to work on ISE 7.1 ?  Thanks in advanced !
	>       >
	>       >Regards,
	>       >
	>       >Zijia
	>       >
	>       >
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	>       >
	>       >
	>       >
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	>      
	>
	> 
	>
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