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RE: [partial-reconfig] illegal connection
Hi, Zijia,
I am not very sure about that.
Are you sure buffers are instantiated and used correctly in your design?
Could you show me your top level design see if I could find something?
Regards
yi lu
Quoting Ye Zijia <yezijia@xxxxxxxxxx>:
> Hi yilu,
> i managed to remove the errors due to IOports but can you tell me
> why is there an error for output port and how to solve it?
>
> I have these declaration at the top level :
>
> FLASH_CEn : OUT STD_LOGIC;
> FLASH_OEn : OUT STD_LOGIC;
> FLASH_WEn : OUT STD_LOGIC;
> SYS_CLK_OUT : OUT STD_LOGIC;
> RAM_CLK : IN STD_LOGIC;
>
> ERROR:NgdBuild:467 - output pad net 'FLASH_OEn_OBUF' has an illegal buffer
>
> ERROR:NgdBuild:467 - output pad net 'FLASH_WEn_OBUF' has an illegal buffer
>
> ERROR:NgdBuild:467 - output pad net 'FLASH_CEn_OBUF' has an illegal buffer
>
> ERROR:NgdBuild:467 - output pad net 'SYS_CLK_OUT_OBUF' has an illegal buffer
>
> ERROR:NgdBuild:455 - logical net 'RAM_CLK_IBUF' has multiple drivers. The
>
> possible drivers causing this are:
>
> pin O on block RAM_CLK_IBUF with type IBUF,
>
> pin PAD on block fix/RAM_CLK_IBUF with type PAD
>
> Regards,
>
> Zijia
>
>
>
> -----Original Message-----
> From: owner-partial-reconfig@xxxxxxxxxxxxxx on behalf of yilu@xxxxxxxxxxxxxx
> Sent: Tue 1/10/2006 11:42 AM
> To: partial-reconfig@xxxxxxxxxxxxxx
> Cc:
> Subject: RE: [partial-reconfig] illegal connection
>
>
>
> Hi, Zijia,
>
> See this file, might be helpful.
>
> http://www.itee.uq.edu.au/~yilu/test_biiobuf.vhd
>
> Cheers,
> yilu
>
>
> Quoting Ye Zijia <yezijia@xxxxxxxxxx>:
>
> > Dear yilu,
> > I have disabled IO insertion for the modules and have
> enabled
> > it at the top level too. Can u give me an example on how to instantiated
> the
> > iobufs and how to do the control logic ?
> >
> > Regards,
> >
> > Zijia
> >
> >
> > -----Original Message-----
> > From: owner-partial-reconfig@xxxxxxxxxxxxxx on behalf of
> yilu@xxxxxxxxxxxxxx
> > Sent: Mon 1/9/2006 4:21 PM
> > To: partial-reconfig@xxxxxxxxxxxxxx
> > Cc:
> > Subject: Re: [partial-reconfig] illegal connection
> >
> >
> >
> > Hi,
> >
> > Hope these links help.
> >
> >
>
>
http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2005/06/msg00034.html
> >
> >
>
>
http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2005/06/msg00035.html
> >
> > Regards,
> > yilu
> >
> > Quoting Ye Zijia <yezijia@xxxxxxxxxx>:
> >
> > > Hi,
> > > can anyone tell me what could be causing these errors and some
> advice
> > on
> > > how to overcome this ? I am using ISE 6.3.
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_8_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_8_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_9_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_9_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_10_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_10_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_11_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_11_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'FPGA_RESET_EN_OBUF' has
> illegal
> > >
> > > connection. Possible pins causing this are:
> > >
> > > pin I on block FPGA_RESET_EN_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_12_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_12_OBUF with type OBUF
> > >
> > > ERROR:NgdBuild:466 - bidirect pad net 'LD_13_OBUF' has illegal
> connection.
> > >
> > > Possible pins causing this are:
> > >
> > > pin I on block LD_13_OBUF with type OBUF
> > >
> > >
> > >
> > > Thanks for all ur time !
> > >
> > > Regards,
> > >
> > > Zijia
> > >
> > > ___________________________
> > > partial-reconfig mailing list
> > > partial-reconfig@xxxxxxxxxxxxxx
> > > Mailing List Archive :
> > http://www.itee.uq.edu.au/~listarch/partial-reconfig/
> > >
> >
> >
> > Lu, Yi
> > School of Info. Tech. and Elec. Eng.
> > The University of Queensland
> > Brisbane 4072 Australia.
> >
> > Phone: +61 7 33658303
> > E-mail: yilu@xxxxxxxxxxxxxx
> >
> > ___________________________
> > partial-reconfig mailing list
> > partial-reconfig@xxxxxxxxxxxxxx
> > Mailing List Archive :
> http://www.itee.uq.edu.au/~listarch/partial-reconfig/
> >
> >
> >
>
>
>
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>
>
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