[partial-reconfig] Reconfiguring columns that have active signals

[Jonathan Jung <jwjung@xxxxxxxxxxxxx>]

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Hi guys,

I've been working on a project for school that involves using the  
microblaze, uClinux, and a HW accelerator for AES.  So far, so good.   
Software's working great, integration between OpenSSL and my hardware  
is fantastic.

Now, I'm expanding my project into the partial re-configurability  
area, but have a couple questions.

1. The way my board is laid out, I have all the pins for memory and  
other stuff on one side of the device.  The pins for serial and  
global reset are on the opposite side.  I've been able to constrain  
my Computer system to the side with the most pins, leaving about 50%  
of the FPGA left for the AES accelerator.

However, either the pins will be included in the reconfigurable  
section, or the wires for the serial port will at least pass through it.

Can I integrate these into the reconfigurable module, and manage them  
using the bus macros like the reset of my signals?  I understand that  
I won't be able to receive or send data (or reset) during that time,  
but has anybody tried anything similar and had their system crash?

2. I'm having trouble reducing the area of the computer system.  It  
starts to expand horizontally, rather than vertically, leaving a lot  
of area unused near the top and bottom of the FPGA.  The AES core  
fills up more vertically than horizontally, which is good for the  
purpose of reconfiguration.  Any tips on restricting the area of the  
microblaze system?

Jonathan
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