Re: [partial-reconfig] Reconfiguring columns that have active signals

[Ivan <salorankatu@xxxxxxxx>]

Hi Jonathan,

I remember that I was talking with you about that in the
MicroBlaze-uCLinux mailing list ;)

About your question, it is posible to cross the boundaries using BM, as
you proposed for your reset and serial port. However, I remember some
problems with that, during the reconfiguration process. In the last
conference where I was, some research works reported something similar
when they have 2 or more dynamic areas. It is not possible the
communication with the second dynamic area if you are reconfiguring the
first one. 

I am not sure about that, because in my work I only had one dynamic
area, and all pins used by the processors were in the fixed module.

Regards,

Ivan

El mié, 01-03-2006 a las 02:56 -0800, Jonathan Jung escribió:
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> Hi guys,
> 
> I've been working on a project for school that involves using the  
> microblaze, uClinux, and a HW accelerator for AES.  So far, so good.   
> Software's working great, integration between OpenSSL and my hardware  
> is fantastic.
> 
> Now, I'm expanding my project into the partial re-configurability  
> area, but have a couple questions.
> 
> 1. The way my board is laid out, I have all the pins for memory and  
> other stuff on one side of the device.  The pins for serial and  
> global reset are on the opposite side.  I've been able to constrain  
> my Computer system to the side with the most pins, leaving about 50%  
> of the FPGA left for the AES accelerator.
> 
> However, either the pins will be included in the reconfigurable  
> section, or the wires for the serial port will at least pass through it.
> 
> Can I integrate these into the reconfigurable module, and manage them  
> using the bus macros like the reset of my signals?  I understand that  
> I won't be able to receive or send data (or reset) during that time,  
> but has anybody tried anything similar and had their system crash?
> 
> 2. I'm having trouble reducing the area of the computer system.  It  
> starts to expand horizontally, rather than vertically, leaving a lot  
> of area unused near the top and bottom of the FPGA.  The AES core  
> fills up more vertically than horizontally, which is good for the  
> purpose of reconfiguration.  Any tips on restricting the area of the  
> microblaze system?
> 
> Jonathan
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