Hi Ivan,Yes, now that I've gotten that part of my project working (hw accel), I've moved over to this list in order to try and get Partial reconfig to work. Unfortunately, I don't have any control over where the traces were laid out on this eval board, so I have no choice but to have the serial and reset wires go through the reconfigurable module. I only have 1 reconfigurable module, so my hope is that when reconfiguring the system, serial data just won't flow.
I know you read the reconfiguration data from the onboard flash, however I'll probably have to use the JTAG port to program from a computer (initial config is handled by ace file) because I don't have flash nor pins connected to the selector switches (unless I modify the board).
>Fortunately VirtexII makes a ROC (Reset on configuration) during the initial >configuration that resets the SCP and makes possible to run the application
>without an external reset button.Indeed, I've never even made use of the reset button for my Microblaze system.
>From my experience is not a good idea to pass peripherals pins from one area to >another through very long lines that cross the whole FPGA. I had many problems
>with those long paths."All" it would take is me reworking the board to have the 3 pins on the other side ;) But I have to work with what I have.
Jonathan On Mar 3, 2006, at 2:28 AM, Ivan wrote:
Hi Jonathan, I remember that I was talking with you about that in the MicroBlaze-uCLinux mailing list ;)About your question, it is posible to cross the boundaries using BM, asyou proposed for your reset and serial port. However, I remember some problems with that, during the reconfiguration process. In the last conference where I was, some research works reported something similar when they have 2 or more dynamic areas. It is not possible thecommunication with the second dynamic area if you are reconfiguring thefirst one. I am not sure about that, because in my work I only had one dynamic area, and all pins used by the processors were in the fixed module. Regards, Ivan
___________________________ partial-reconfig mailing list partial-reconfig@xxxxxxxxxxxxxx Mailing List Archive : http://www.itee.uq.edu.au/~listarch/partial-reconfig/