Re: [partial-reconfig] Virtex-4 slice-based bus macros

["valerios" <valerios@xxxxxxxxxx>]

Many Thanks Pete Sedcole!

Whether it is needed to add here yet *cfg "_NET_PROP::IS_BUS_MACRO:" * ?
Does the "Enable" entrance serve in order that during replacement of the 
module temporally to disconnect BUS ?


Is creating a project possible only with the EDIF files (as done in xapp290) 
?
Is it possible to create a project not from EDIF-files?
Than better to recode VHDL->EDIF?
In xapp290 alike used "Synplify" (version "6.2.0, Build 083R").
Synplify, Synplify Pro, and Synplify Premier 8.5 Production Software for 
Windows (165830300 bytes)
Are there the programs a little less?
How to do something alike, but from VHDL-files?

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