Re: [partial-reconfig] Virtex-4 slice-based bus macros

["valerios" <valerios@xxxxxxxxxx>]

Pete Sedcole wrote:

> > Is creating a project possible only with the EDIF files (as done in 
> > xapp290) ?
> > Is it possible to create a project not from EDIF-files?
> > Than better to recode VHDL->EDIF?
> I'm not sure what you mean here. EDIF is a netlist format: you'll use it 
> if you synthesize using Synplify. If you use XST to synthesize the netlist 
> format is different. Shouldn't make a difference.
> > In xapp290 alike used "Synplify" (version "6.2.0, Build 083R").
> > Synplify, Synplify Pro, and Synplify Premier 8.5 Production Software for 
> > Windows (165830300 bytes)
> > Are there the programs a little less?
> I've used XST with no problem.
> > How to do something alike, but from VHDL-files?
> Do you mean making a macro from VHDL files? It may be possible, but I 
> don't really know.

I work with ISE 6.3.
Did I mean that how necessarily to use the EDIF files for work with PR (how 
did in xapp290) ?
Is it possible successfully to work with VHDL ?
Or necessarily must all files be in the EDIF format?
Is it possible successfully to work with PR and VHDL (not EDIF) ?
I know how to work with PR (on xapp290) only on the basis of the EDIF files.
Is it possible to do PR not passing to the EDIF format?
If yes, as?

Forgive please for my English.

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