valerios wrote:
I work with ISE 6.3.Did I mean that how necessarily to use the EDIF files for work with PR (how did in xapp290) ?Is it possible successfully to work with VHDL ? Or necessarily must all files be in the EDIF format? Is it possible successfully to work with PR and VHDL (not EDIF) ?I know how to work with PR (on xapp290) only on the basis of the EDIF files.Is it possible to do PR not passing to the EDIF format? If yes, as?
Ok, it sounds like you know how to run PR if you have EDIF files, but you want to know if you can start from VHDL and avoid using EDIF.
I guess this is possible. Starting with VHDL, synthesize using XST, and produce NGC files (the Xilinx netlist format). Then use the NGC files as you would EDIF. I think that the XAPP290 example has synthesis directives for Synplify in Verilog, which you'd need to replace with the equivalent XST directives in VHDL.
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