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[partial-reconfig] uClinux ICAP driver
Hi everybody,
Find attached a patch that adds the opb_icap driver to MicroBlaze / uClinux.
I haven't used this in a while, apart from confirming that it applies
cleanly to the current CVS head of the uClinux kernel tree.
Any issues, and patches please discuss them here.
Note that getting this to work on PPC Linux should be pretty trivial -
left as an exercise for the reader.
For details on the design and use of the driver, see my paper on the
subject:
http://eprint.uq.edu.au/archive/00001296/
If you are publishing any work that arises from or makes use of this,
please include a reference to the paper. Citations are the hard
currency of research impact! If you do something cool with it, please
let me know. And if you make any money from it, buy me a beer some day.
Thanks.
I have no idea if it works with Virtex4. At the very least, the
opb_hwicap EDK peripheral doesn't list V4 in the supported architectures
in the MPD file. That may be because it can't work (ICAP is different
maybe?), or the core just hasn't been updated, or something else
entirely. Hack on it, see what you can do. The driver is open source,
and the opb_hwicap core source is visible, so get to it!
Regards,
John
Index: include/asm-microblaze/xhwicap_ioctl.h
===================================================================
--- include/asm-microblaze/xhwicap_ioctl.h (revision 0)
+++ include/asm-microblaze/xhwicap_ioctl.h (revision 486)
@@ -0,0 +1,12 @@
+#ifndef XHWICAP_IOCTL_H
+#define XHWICAP_IOCTL_H
+
+#include <linux/ioctl.h>
+
+#define XHWICAP_IOC_MAGIC 'i'
+
+#define XHWICAP_IOCCMDDESYNC _IO(XHWICAP_IOC_MAGIC, 1)
+#define XHWICAP_IOCCMDCAPTURE _IO(XHWICAP_IOC_MAGIC, 2)
+#define XHWICAP_IOCGETINST _IO(XHWICAP_IOC_MAGIC, 3)
+
+#endif
Index: drivers/misc/xilinx_hwicap/adapter.c
===================================================================
--- drivers/misc/xilinx_hwicap/adapter.c (revision 0)
+++ drivers/misc/xilinx_hwicap/adapter.c (revision 486)
@@ -0,0 +1,470 @@
+/*
+ * adapter.c
+ *
+ * Xilinx HWICAP interface to Linux
+ *
+ * Author: John Williams <jwilliams@xxxxxxxxxxxxxx>
+ *
+ * 2004-2006 (c) John Williams. This file is licensed under the
+ * terms of the GNU General Public License version 2.1. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * This driver is a wrapper around the Xilinx level-0 drivers, and opb_hwicap
+ * core. It creates a Linux misc device, minor number 200, that should
+ * be given a dev node something like /dev/icap
+ *
+ * It's simple, cat a partial bitstream to /dev/icap, and voila!
+ *
+ * Of course, since you are reconfiguring the same FPGA that contains the CPU,
+ * and busses, and operating system, and in fact everything, the potential for
+ * catastrophic failure is high.
+ *
+ * With sufficient bad luck, determination or aliean technology you may even
+ * damange the FPGA with it. If so, please tell me, so we can have a good
+ * over it some day. But, don't call your lawyer, or my lawyer - it's not
+ * my fault.
+ *
+ * Finally, if you publish anything that builds on, or makes use of this driver,
+ * or if you just feel like being generous with citations, please reference
+ * the original paper where I described the idea:
+ *
+ * Williams, John A. and Bergmann, Neil W. (2004) "Embedded Linux as a Platform
+ * for Dynamically Self-Reconfiguring Systems-On-Chip". In Engineering of
+ * Reconfigurable Systems and Algorithms (ERSA 2004), 21-24 June, 2004,
+ * Las Vegas, Nevada, USA.
+ *
+ * You might also like to read it, to get a better idea of what I was thinking.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/miscdevice.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include <linux/autoconf.h>
+
+#include "xbasic_types.h"
+#include "xhwicap.h"
+#include "xhwicap_i.h"
+#include <asm/xhwicap_ioctl.h>
+
+MODULE_AUTHOR("John Williams <jwilliams@xxxxxxxxxxxxxx");
+MODULE_DESCRIPTION("Xilinx HWICAP driver");
+MODULE_LICENSE("GPL");
+
+#if 0
+#define DBPRINTK(...) printk(__VA_ARGS__)
+#else
+#define DBPRINTK(...)
+#endif
+
+#define ASSERT(x) { if(!(x)) printk("Assertion failed: ## x ## :%s:%s:%i\n",__FUNCTION__,__FILE__,__LINE__);}
+
+/* Our private per interface data. */
+struct xhwicap_instance {
+ struct xhwicap_instance *next_inst; /* The next instance in inst_list */
+ int index; /* Which interface is this */
+ u32 save_BaseAddress; /* Saved physical base address */
+ XHwIcap HwIcap;
+ unsigned int pendingWord;
+ unsigned pendingByteCount;
+};
+/* List of instances we're handling. */
+static struct xhwicap_instance *inst_list = NULL;
+
+static int
+xhwicap_open(struct inode *inode, struct file *file)
+{
+ struct xhwicap_instance *inst;
+
+ MOD_INC_USE_COUNT;
+
+ /* FIXME assume head of list is the only instance */
+ inst = inst_list;
+
+ inst->pendingWord=0;
+ inst->pendingByteCount=0;
+
+ return 0;
+}
+
+static int
+xhwicap_release(struct inode *inode, struct file *file)
+{
+ MOD_DEC_USE_COUNT;
+
+ return 0;
+}
+
+#if 0
+static xhwicap_instance *
+ioctl_getinstance(unsigned long arg,
+ void **userdata,
+ struct xhwicap_instance **match)
+{
+ struct xhwicap_instance *inst;
+
+ if (copy_from_user(ioctl_data, (void *) arg, sizeof (*ioctl_data)))
+ return -EFAULT;
+
+ inst = inst_list;
+ while (inst && inst->index != ioctl_data->device)
+ inst = inst->next_inst;
+
+ *match = inst;
+ return inst ? 0 : -ENODEV;
+}
+#endif
+
+
+static int
+xhwicap_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct xhwicap_instance *inst;
+ XStatus status;
+
+ /* FIXME! Assume instance is first in list - this is bogus */
+ inst = inst_list;
+ if(!inst)
+ return -ENODEV;
+
+ switch (cmd) {
+ case XHWICAP_IOCCMDDESYNC:
+ DBPRINTK("desynch()\n");
+ status = XHwIcap_CommandDesync(&(inst->HwIcap));
+ if(status==XST_DEVICE_BUSY)
+ return -EBUSY;
+ break;
+
+ case XHWICAP_IOCCMDCAPTURE:
+ DBPRINTK("capture()\n");
+ status = XHwIcap_CommandCapture(&(inst->HwIcap));
+ if(status==XST_DEVICE_BUSY)
+ return -EBUSY;
+ break;
+
+ case XHWICAP_IOCGETINST:
+ DBPRINTK("getinst()\n");
+ copy_to_user((void *)arg, (void *)(&(inst->HwIcap)), sizeof(XHwIcap));
+
+ default:
+ return -ENOIOCTLCMD;
+
+ }
+ return 0;
+}
+
+/* Method to read data from hwicap device and copy into user buffer */
+/* Do the read in fixed size chunks */
+
+static ssize_t
+xhwicap_read(struct file *filp, char *buf, size_t count, loff_t *f_pos)
+{
+ struct xhwicap_instance *inst;
+ size_t read_count=count;
+ XStatus status;
+ int wordCount=0;
+ char *user_ptr=buf;
+
+ DBPRINTK("xhwicap_read\n");
+
+ /* FIXME! Assume instance is first in list - this is bogus */
+ inst = inst_list;
+ if(!inst)
+ return -ENODEV;
+
+ DBPRINTK("reading %i words from device\n",(count+3)>>2);
+
+ while(read_count)
+ {
+ int chunk_word_count;
+ size_t chunk_size, chunk_left;
+
+ /* Work out how big this chunk should be */
+ chunk_size=min(read_count, (size_t)XHI_MAX_BUFFER_BYTES);
+ chunk_word_count=0;
+
+ DBPRINTK("chunk size %lX\n",chunk_size);
+
+ /* Read the chunk from the device */
+ status = XHwIcap_DeviceRead(&(inst->HwIcap), 0, (chunk_size+3)>>2);
+ /* Check return status */
+ if(status==XST_BUFFER_TOO_SMALL)
+ return -ENOSPC;
+ else if(status==XST_DEVICE_BUSY)
+ return -EBUSY;
+ else if(status==XST_INVALID_PARAM)
+ return -EINVAL;
+
+ DBPRINTK("read chunk from device\n");
+
+ /* Copy this chunk from private buffer into user space */
+ chunk_left = chunk_size;
+
+ /* Copy from device private buffer into user buffer */
+ DBPRINTK("copying chunk to user buffer\n");
+ while(chunk_left)
+ {
+ size_t bytesToWrite=min((size_t)4, chunk_left);
+ u32 tmp=XHwIcap_StorageBufferRead(&(inst->HwIcap),chunk_word_count);
+
+ copy_to_user(user_ptr,&tmp, bytesToWrite);
+ user_ptr += bytesToWrite;
+ chunk_left -=bytesToWrite;
+ chunk_word_count++;
+ }
+ read_count-=chunk_size;
+ }
+ DBPRINTK("done\n");
+
+ return count-read_count;
+}
+
+static ssize_t
+xhwicap_write(struct file *filp, const char *buf, size_t count, loff_t *f_pos)
+{
+ struct xhwicap_instance *inst;
+ size_t write_count=count;
+ XStatus status;
+ const char *user_buf=buf;
+
+ DBPRINTK("write\n");
+ DBPRINTK("count is %lX\n",count);
+
+ /* FIXME! Assume instance is first in list - this is bogus */
+ inst = inst_list;
+ if(!inst)
+ return -ENODEV;
+
+ /* Deal with any left overs from last time */
+ DBPRINTK("PREAMBLE: %i bytes pending\n",inst->pendingByteCount);
+
+ ASSERT(inst->pendingByteCount<4);
+
+ /* Only enter the preamble if there is stuff left from last time */
+ while(inst->pendingByteCount && inst->pendingByteCount<4
+ && write_count)
+ {
+ unsigned char tmp;
+ /* Accumulate into the pendingWord */
+ copy_from_user(&tmp, user_buf++, 1);
+ inst->pendingWord=(inst->pendingWord) << 8 | (tmp & 0xFF);
+ inst->pendingByteCount++;
+ write_count--;
+ }
+
+ /* Did we accumulated a full word? */
+ if(inst->pendingByteCount==4)
+ {
+ DBPRINTK("Writing pendingword\n");
+ /* Write the word to the buffer */
+ XHwIcap_StorageBufferWrite(&(inst->HwIcap),0,inst->pendingWord);
+ XHwIcap_DeviceWrite(&(inst->HwIcap), 0, 1);
+ inst->pendingByteCount=0;
+ inst->pendingWord=0;
+ }
+
+ ASSERT(write_count==0 || inst->pendingByteCount==0);
+
+ /* Minimum possible chunk size is 4 bytes */
+ while(write_count>3)
+ {
+ int chunk_word_count=0;
+ size_t chunk_size, chunk_left;
+
+ /* don't use full limit of BUFFER_BYTES, seems to
+ break the hardware..
+ Round down to nearest multiple of 4 */
+ chunk_size=chunk_left=min(write_count,
+ (size_t)XHI_MAX_BUFFER_BYTES-8) & ~0x3;
+
+ DBPRINTK("chunk size %lX\n",chunk_size);
+ DBPRINTK("copying chunk to buffer\n");
+
+ while(chunk_left)
+ {
+ u32 tmp;
+ copy_from_user(&tmp, user_buf, 4);
+ XHwIcap_StorageBufferWrite(&(inst->HwIcap),
+ chunk_word_count++,
+ tmp);
+ user_buf+=4;
+ chunk_left-=4;
+ }
+
+ ASSERT(chunk_word_count);
+
+ DBPRINTK("done\nWriting chunk to device..");
+
+ /* initiate write of private buffer to device */
+ DBPRINTK("chunk_word_count:%X\n",chunk_word_count);
+
+ status = XHwIcap_DeviceWrite(&(inst->HwIcap),
+ 0, chunk_word_count);
+
+ if(status==XST_BUFFER_TOO_SMALL)
+ return -ENOSPC;
+ else if(status==XST_DEVICE_BUSY)
+ return -EBUSY;
+ else if(status==XST_INVALID_PARAM)
+ return -EINVAL;
+
+ write_count-=chunk_word_count*4;
+ }
+
+
+ DBPRINTK("POSTAMBLE: %i bytes remaining\n",write_count);
+
+ ASSERT(write_count<4); /* No more than 3 bytes remaining */
+ /*ASSERT(inst->pendingByteCount==0); *//* pending buffer is empty */
+
+ /* Put remaining bytes into the pending buffer */
+ while(write_count)
+ {
+ unsigned char tmp;
+ copy_from_user(&tmp, user_buf++, 1);
+ inst->pendingWord=(inst->pendingWord) << 8 | (tmp & 0xFF);
+ write_count--;
+ inst->pendingByteCount++;
+ }
+
+ DBPRINTK("finished\n");
+ return count-write_count;
+}
+
+
+static void
+remove_head_inst(void)
+{
+ struct xhwicap_instance *inst;
+ XHwIcap_Config *cfg;
+
+ /* Pull the head off of inst_list. */
+ inst = inst_list;
+ inst_list = inst->next_inst;
+
+ cfg = XHwIcap_LookupConfig(inst->index);
+ iounmap((void *) cfg->BaseAddress);
+ cfg->BaseAddress = inst->save_BaseAddress;
+}
+
+static struct file_operations xfops = {
+ owner:THIS_MODULE,
+ ioctl:xhwicap_ioctl,
+ open:xhwicap_open,
+ release:xhwicap_release,
+ read:xhwicap_read,
+ write:xhwicap_write
+};
+/*
+ * We get to the HWICAP through one minor number. Here's the
+ * miscdevice that gets registered for that minor number.
+ */
+#define HWICAP_MINOR 200
+
+static struct miscdevice miscdev = {
+ minor:HWICAP_MINOR,
+ name:"xhwicap",
+ fops:&xfops
+};
+
+static int __init
+probe(int index)
+{
+ static const unsigned long remap_size
+ = CONFIG_XILINX_HWICAP_0_HIGHADDR - CONFIG_XILINX_HWICAP_0_BASEADDR + 1;
+ struct xhwicap_instance *inst;
+ XHwIcap_Config *cfg;
+
+ /* Find the config for our instance. */
+ cfg = XHwIcap_LookupConfig(index);
+ if (!cfg)
+ return -ENODEV;
+
+ /* Allocate the inst and zero it out. */
+ inst = (struct xhwicap_instance *) kmalloc(sizeof (struct xhwicap_instance),
+ GFP_KERNEL);
+ if (!inst) {
+ printk(KERN_ERR "%s #%d: Could not allocate instance.\n",
+ miscdev.name, index);
+ return -ENOMEM;
+ }
+ memset(inst, 0, sizeof (struct xhwicap_instance));
+ inst->index = index;
+
+ /* Make it the head of inst_list. */
+ inst->next_inst = inst_list;
+ inst_list = inst;
+
+ /* Change the addresses to be virtual; save the old ones to restore. */
+ inst->save_BaseAddress = cfg->BaseAddress;
+ cfg->BaseAddress = (u32) ioremap(inst->save_BaseAddress, remap_size);
+
+ /* Tell the Xilinx code to bring this HWICAP interface up. */
+ /* REALLY FIXME - XC2V1000 is hard coded - bleugh! */
+ if (XHwIcap_Initialize(&inst->HwIcap, cfg->DeviceId,
+ XHI_XC2V1000) != XST_SUCCESS) {
+ printk(KERN_ERR "%s #%d: Could not initialize instance.\n",
+ miscdev.name, inst->index);
+ remove_head_inst();
+ return -ENODEV;
+ }
+
+ printk(KERN_INFO "%s #%d at 0x%08X mapped to 0x%08X\n",
+ miscdev.name, inst->index,
+ inst->save_BaseAddress, cfg->BaseAddress);
+
+ return 0;
+}
+
+static int __init
+xhwicap_init(void)
+{
+ int rtn, index = 0;
+
+ printk("probing...\n");
+ while (probe(index++) == 0) ;
+
+ if (index > 1) {
+ /* We found at least one instance. */
+
+ /* Register the driver with misc and report success. */
+ rtn = misc_register(&miscdev);
+ if (rtn) {
+ printk(KERN_ERR "%s: Could not register driver.\n",
+ miscdev.name);
+ while (inst_list)
+ remove_head_inst();
+ return rtn;
+ }
+
+ /* Report success. */
+ printk("Xilinx HWICAP registered\n");
+ return 0;
+ } else {
+ /* No instances found. */
+ printk("Probe failed\n");
+ return -ENODEV;
+ }
+}
+
+static void __exit
+xhwicap_cleanup(void)
+{
+ while (inst_list)
+ remove_head_inst();
+
+ misc_deregister(&miscdev);
+}
+
+EXPORT_NO_SYMBOLS;
+
+module_init(xhwicap_init);
+module_exit(xhwicap_cleanup);
Index: drivers/misc/xilinx_hwicap/xhwicap_i.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_i.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_i.h (revision 486)
@@ -0,0 +1,243 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_i.h,v 1.4 2003/12/23 23:15:03 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_i.h
+*
+* This head file contains internal identifiers, which are those shared
+* between the files of the driver. It is intended for internal use
+* only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/14/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_I_H_ /* prevent circular inclusions */
+#define XHWICAP_I_H_ /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+
+
+/************************** Constant Definitions ****************************/
+
+
+#define XHI_PAD_FRAMES 0x1
+
+/* Mask for calculating configuration packet headers */
+#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
+#define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
+#define XHI_TYPE_MASK 0x7
+#define XHI_REGISTER_MASK 0xF
+#define XHI_OP_MASK 0x3
+#define XHI_FAR_BLOCK_MASK 0x3
+#define XHI_FAR_MAJOR_FRAME_MASK 0xFF
+#define XHI_FAR_MINOR_FRAME_MASK 0xFF
+
+#define XHI_TYPE_SHIFT 29
+#define XHI_REGISTER_SHIFT 13
+#define XHI_OP_SHIFT 27
+#define XHI_FAR_BLOCK_SHIFT 25
+#define XHI_FAR_MAJOR_FRAME_SHIFT 17
+#define XHI_FAR_MINOR_FRAME_SHIFT 9
+
+#define XHI_TYPE_1 1
+#define XHI_TYPE_2 2
+#define XHI_OP_WRITE 2
+#define XHI_OP_READ 1
+
+/* Address Block Types */
+#define XHI_FAR_CLB_BLOCK 0
+#define XHI_FAR_BRAM_BLOCK 1
+#define XHI_FAR_BRAM_INT_BLOCK 2
+
+/* Addresses of the Configuration Registers */
+#define XHI_CRC 0
+#define XHI_FAR 1
+#define XHI_FDRI 2
+#define XHI_FDRO 3
+#define XHI_CMD 4
+#define XHI_CTL 5
+#define XHI_MASK 6
+#define XHI_STAT 7
+#define XHI_LOUT 8
+#define XHI_COR 9
+#define XHI_MFWR 10
+#define XHI_FLR 11
+#define XHI_KEY 12
+#define XHI_CBC 13
+#define XHI_IDCODE 14
+#define XHI_NUM_REGISTERS 15
+
+/* Configuration Commands */
+#define XHI_CMD_WCFG 1
+#define XHI_CMD_MFW 2
+#define XHI_CMD_DGHIGH 3
+#define XHI_CMD_RCFG 4
+#define XHI_CMD_START 5
+#define XHI_CMD_RCAP 6
+#define XHI_CMD_RCRC 7
+#define XHI_CMD_AGHIGH 8
+#define XHI_CMD_SWITCH 9
+#define XHI_CMD_GRESTORE 10
+#define XHI_CMD_SHUTDOWN 11
+#define XHI_CMD_GCAPTURE 12
+#define XHI_CMD_DESYNCH 13
+
+/* Packet constants */
+#define XHI_SYNC_PACKET 0xAA995566UL
+#define XHI_DUMMY_PACKET 0xFFFFFFFFUL
+#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
+#define XHI_TYPE_2_READ ( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
+ (XHI_OP_READ << XHI_OP_SHIFT) )
+
+#define XHI_TYPE_2_WRITE ( (XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
+ (XHI_OP_WRITE << XHI_OP_SHIFT) )
+
+#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
+#define XHI_TYPE_1_HEADER_BYTES 4
+#define XHI_TYPE_2_HEADER_BYTES 8
+
+/* Indicates how many bytes will fit in a buffer. (1 BRAM) */
+#define XHI_MAX_BUFFER_BYTES 2048
+#define XHI_MAX_BUFFER_INTS 512
+
+/* Number of frames in different tile types */
+#define XHI_GCLK_FRAMES 4
+#define XHI_IOB_FRAMES 4
+#define XHI_IOI_FRAMES 22
+#define XHI_CLB_FRAMES 22
+#define XHI_BRAM_FRAMES 64
+#define XHI_BRAM_INT_FRAMES 22
+
+/* The number of words reserved for the header in the storage buffer. */
+#define XHI_HEADER_BUFFER_WORDS 20
+#define XHI_HEADER_BUFFER_BYTES (XHI_HEADER_BUFFER_WORDS << 2)
+
+/* CLB major frames start at 3 for the first column (since we are using
+ * column numbers that start at 1, when the column is added to this offset,
+ * that first one will be 3 as required. */
+#define XHI_CLB_MAJOR_FRAME_OFFSET 2
+
+
+/* File access and error constants */
+#define XHI_DEVICE_READ_ERROR -1
+#define XHI_DEVICE_WRITE_ERROR -2
+#define XHI_BUFFER_OVERFLOW_ERROR -3
+
+#define XHI_DEVICE_READ 0x1
+#define XHI_DEVICE_WRITE 0x0
+
+/* Constants for checking transfer status */
+#define XHI_CYCLE_DONE 0
+#define XHI_CYCLE_EXECUTING 1
+
+/* Constant to use for CRC check when CRC has been disabled */
+#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
+
+/* Major Row Offset */
+#define XHI_CLB_MAJOR_ROW_OFFSET 96+(32*XHI_HEADER_BUFFER_WORDS)-1
+
+/* Number of times to poll the done regsiter */
+#define XHI_MAX_RETRIES 1000
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that reads back the requested configuration
+* register.
+*
+* @param Register is the address of the register to be read back.
+* Register constants are defined in this file.
+*
+* @return Type 1 packet header to read the specified register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XHwIcap_Type1Read(Register) \
+ ( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
+ (XHI_OP_READ << XHI_OP_SHIFT) )
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that writes to the requested
+* configuration register.
+*
+* @param Register is the address of the register to be written to.
+* Register constants are defined in this file.
+*
+* @return Type 1 packet header to write the specified register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XHwIcap_Type1Write(Register) \
+ ( (XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
+ (XHI_OP_WRITE << XHI_OP_SHIFT) )
+
+/****************************************************************************/
+/**
+*
+* Generates a Type 1 packet header that writes to the FAR (Frame Address
+* Register).
+*
+* @param Block - Address Block Type (CLB or BRAM address space)
+*
+* @param MajorAddress - CLB or BRAM column
+*
+* @param MinorAdderss - Frame within column
+*
+* @return Type 1 packet header to write the FAR
+*
+* @note None.
+*
+*****************************************************************************/
+#define XHwIcap_SetupFar(Block, MajorAddress, MinorAddress) \
+ ((Block << XHI_FAR_BLOCK_SHIFT) | \
+ (MajorAddress << XHI_FAR_MAJOR_FRAME_SHIFT) | \
+ (MinorAddress << XHI_FAR_MINOR_FRAME_SHIFT))
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/* the configuration table */
+extern XHwIcap_Config XHwIcap_ConfigTable[];
+
+#endif
Index: drivers/misc/xilinx_hwicap/xhwicap_clb_ff.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_clb_ff.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_clb_ff.h (revision 486)
@@ -0,0 +1,275 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_clb_ff.h,v 1.5 2003/12/10 16:52:45 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
+* INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_ff.h
+*
+* This header file contains bit information about the CLB FF resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/14/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_CLB_FF_H_ /* prevent circular inclusions */
+#define XHWICAP_CLB_FF_H_ /* by using protection macros */
+
+/************************** Constant Definitions ****************************/
+
+/** Index into the CONTENTS and SRMODE for XQ Register. */
+#define XHI_CLB_XQ 0
+/** Index into the CONTENTS and SRMODE for YQ Register. */
+#define XHI_CLB_YQ 1
+
+/**************************** Type Definitions ******************************/
+
+typedef struct
+{
+
+ /* MODE values. */
+ const u8 LATCH[1]; /* Value to put register into LATCH mode. */
+ const u8 FF[1]; /* Value to put register into FF mode. */
+
+ /* CONTENTS values. */
+ const u8 INIT0[1]; /* Value to initialize register CONTENTS to 0. */
+ const u8 INIT1[1]; /* Value to initialize register CONTENTS to 1. */
+ const u8 ZERO[1]; /* Same as INIT0 */
+ const u8 ONE[1]; /* Same as INIT1 */
+
+ /* SRMODE values. */
+ const u8 SRLOW[1]; /* When SR is asserted register goes to 0 (resets). */
+ const u8 SRHIGH[1]; /* When SR is asserted register goes to 1 (sets). */
+
+ /* SYNCMODE values. */
+ const u8 SYNC[1]; /* Puts both XQ and YQ in synchronous set/reset
+ mode. */
+ const u8 ASYNC[1]; /* Puts both XQ and YQ in asynchronous
+ set/reset mode. */
+
+ /* LATCH or FF mode. Indexed by slice (0-3) only. It affects both
+ * XQ and YQ registers. */
+ const u8 MODE[4][1][2];
+
+ /** SYNC or ASYNC mode. Indexed by slice (0-3) only. It affects
+ * both XQ and YQ registers. */
+ const u8 SYNCMODE[4][1][2];
+
+ /* INIT0, INIT1, ONE, or ZERO. Indexed by the slice basis (0-3).
+ * And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ).
+ * INIT0 and ZERO are equivalent as well as INIT1 and ONE. There
+ * are two values there only as to not confuse the values given in
+ * FPGA_EDITOR which are INIT0 and INIT1. They both can either
+ * initialize or directly set the Register contents (assuming a
+ * GRESTORE packet command is used after doing a configuration on a
+ * device). */
+ const u8 CONTENTS[4][2][1][2];
+
+ /* SRHIGH or SRLOW. Indexed by the slice (0-3).
+ * And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ)
+ */
+ const u8 SRMODE[4][2][1][2];
+
+} XHwIcap_ClbFf;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/***************************************************************************/
+/**
+* This structure defines the bits associated with a Flip Flop in a CLB
+* tile. Note that there are 8 FFs, the XQ and YQ Registers in
+* Slice 0, 1, 2 and 3.
+*/
+const XHwIcap_ClbFf XHI_CLB_FF =
+{
+ /* LATCH*/
+ {1},
+ /* FF*/
+ {0},
+ /* INIT0*/
+ {1},
+ /* INIT1*/
+ {0},
+ /* ZERO*/
+ {1},
+ /* ONE*/
+ {0},
+ /* SRLOW*/
+ {1},
+ /* SRHIGH*/
+ {0},
+ /* SYNC*/
+ {1},
+ /* ASYNC*/
+ {0},
+ /* MODE*/
+ {
+ /* Slice 0. */
+ {
+ {4, 0}
+ },
+ /* Slice 1. */
+ {
+ {44, 0}
+ },
+ /* Slice 2. */
+ {
+ {35, 0}
+ },
+ /* Slice 3. */
+ {
+ {75, 0}
+ }
+ },
+ /* SYNCMODE*/
+ {
+ /* Slice 0. */
+ {
+ {16, 0}
+ },
+ /* Slice 1. */
+ {
+ {56, 0}
+ },
+ /* Slice 2. */
+ {
+ {23, 0}
+ },
+ /* Slice 3. */
+ {
+ {63, 0}
+ }
+ },
+ /* CONTENTS*/
+ {
+ /* Slice 0. */
+ {
+ /* LE 0. */
+ {
+ {17, 1}
+ },
+ /* LE 1. */
+ {
+ {17, 2}
+ }
+ },
+ /* Slice 1. */
+ {
+ /* LE 0. */
+ {
+ {57, 1}
+ },
+ /* LE 1. */
+ {
+ {57, 2}
+ }
+ },
+ /* Slice 2. */
+ {
+ /* LE 0. */
+ {
+ {19, 1}
+ },
+ /* LE 1. */
+ {
+ {19, 2}
+ }
+ },
+ /* Slice 3. */
+ {
+ /* LE 0. */
+ {
+ {59, 1}
+ },
+ /* LE 1. */
+ {
+ {59, 2}
+ }
+ }
+ },
+ /* SRMODE*/
+ {
+ /* Slice 0. */
+ {
+ /* LE 0. */
+ {
+ {0, 0}
+ },
+ /* LE 1. */
+ {
+ {15, 0}
+ }
+ },
+ /* Slice 1. */
+ {
+ /* LE 0. */
+ {
+ {40, 0}
+ },
+ /* LE 1. */
+ {
+ {55, 0}
+ }
+ },
+ /* Slice 2. */
+ {
+ /* LE 0. */
+ {
+ {39, 0}
+ },
+ /* LE 1. */
+ {
+ {24, 0}
+ }
+ },
+ /* Slice 3. */
+ {
+ /* LE 0. */
+ {
+ {79, 0}
+ },
+ /* LE 1. */
+ {
+ {64, 0}
+ }
+ }
+ },
+
+};
+
+#endif
Index: drivers/misc/xilinx_hwicap/xhwicap_l.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_l.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_l.h (revision 486)
@@ -0,0 +1,250 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_l.h,v 1.5 2003/12/10 16:52:45 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device. High-level driver functions
+* are defined in xhwicap.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/14/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_L_H_ /* prevent circular inclusions */
+#define XHWICAP_L_H_ /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions ****************************/
+
+/* XHwIcap register offsets */
+
+#define XHI_SIZE_REG_OFFSET 0x800L /* Size of transfer, read & write */
+#define XHI_BRAM_OFFSET_REG_OFFSET 0x804L /* Offset into bram, read & write */
+#define XHI_RNC_REG_OFFSET 0x808L /* Read not Configure, direction of
+ transfer. Write only */
+#define XHI_DONE_REG_OFFSET 0x80CL /* Indicates transfer complete. Read
+ only */
+
+/* Constants for setting the RNC register */
+#define XHI_CONFIGURE 0x0UL
+#define XHI_READBACK 0x1UL
+
+/* Constants for the Done register */
+#define XHI_NOT_FINISHED 0x0UL
+#define XHI_FINISHED 0x1UL
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the size register.
+*
+* The size register holds the number of 32 bit words to transfer between
+* bram and the icap (or icap to bram).
+*
+* @param BaseAddress is the base address of the device
+*
+* @return A 32-bit value representing the contents of the size
+* register.
+*
+* @note
+*
+* u32 XHwIcap_mGetSizeReg(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XHwIcap_mGetSizeReg(BaseAddress) \
+ ( XIo_In32((BaseAddress) + XHI_SIZE_REG_OFFSET) )
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the bram offset register.
+*
+* The bram offset register holds the starting bram address to transfer
+* data from during configuration or write data to during readback.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return A 32-bit value representing the contents of the bram offset
+* register.
+*
+* @note
+*
+* u32 XHwIcap_mGetOffsetReg(u32 BaseAddress);
+*
+*****************************************************************************/
+#define XHwIcap_mGetOffsetReg(BaseAddress) \
+ ( XIo_In32((BaseAddress + XHI_BRAM_OFFSET_REG_OFFSET)) )
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the done register.
+*
+* The done register is set to zero during configuration or readback.
+* When the current configuration or readback completes the done register
+* is set to one.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return A 32-bit value representing the contents of the bram offset
+* register.
+*
+* @note
+*
+* u32 XHwIcap_mGetDoneReg(u32 BaseAddress);
+*
+*****************************************************************************/
+
+#define XHwIcap_mGetDoneReg(BaseAddress) \
+ ( XIo_In32((BaseAddress + XHI_DONE_REG_OFFSET)) )
+
+/****************************************************************************/
+/**
+* Reads data from the storage buffer bram.
+*
+* A bram is used as a configuration memory cache. One frame of data can
+* be stored in this "storage buffer".
+*
+* @param BaseAddress - contains the base address of the component.
+*
+* @param Offset - The offset into which the data should be read.
+*
+* @return The value of the specified offset in the bram.
+*
+* @note
+*
+* u32 XHwIcap_mGetBram(u32 BaseAddress, u32 Offset);
+*
+*****************************************************************************/
+#define XHwIcap_mGetBram(BaseAddress, Offset) \
+ ( XIo_In32((BaseAddress+(Offset<<2))) )
+
+
+
+/****************************************************************************/
+/**
+* Set the size register.
+*
+* The size register holds the number of 8 bit bytes to transfer between
+* bram and the icap (or icap to bram).
+*
+* @param BaseAddress - contains the base address of the device.
+*
+* @param Data - The size in bytes.
+*
+* @return None.
+*
+* @note
+*
+* void XHwIcap_mSetSizeReg(u32 BaseAddress, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_mSetSizeReg(BaseAddress, Data) \
+ ( XIo_Out32((BaseAddress) + XHI_SIZE_REG_OFFSET, (Data)) )
+
+/****************************************************************************/
+/**
+* Set the bram offset register.
+*
+* The bram offset register holds the starting bram address to transfer
+* data from during configuration or write data to during readback.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param Data is the value to be written to the data register.
+*
+* @return None.
+*
+* @note
+*
+* void XHwIcap_mSetOffsetReg(u32 BaseAddress, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_mSetOffsetReg(BaseAddress, Data) \
+ ( XIo_Out32((BaseAddress) + XHI_BRAM_OFFSET_REG_OFFSET, (Data)) )
+
+/****************************************************************************/
+/**
+* Set the RNC (Readback not Configure) register.
+*
+* The RNC register determines the direction of the data transfer. It
+* controls whether a configuration or readback take place. Writing to
+* this register initiates the transfer. A value of 1 initiates a
+* readback while writing a value of 0 initiates a configuration.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @param Data is the value to be written to the data register.
+*
+* @return None.
+*
+* @note
+*
+* void XHwIcap_mSetRncReg(u32 BaseAddress, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_mSetRncReg(BaseAddress, Data) \
+ ( XIo_Out32((BaseAddress) + XHI_RNC_REG_OFFSET, (Data)) )
+
+/****************************************************************************/
+/**
+* Write data to the storage buffer bram.
+*
+* A bram is used as a configuration memory cache. One frame of data can
+* be stored in this "storage buffer".
+*
+* @param BaseAddress - contains the base address of the component.
+*
+* @param Offset - The offset into which the data should be written.
+*
+* @param Data - The value to be written to the bram offset.
+*
+* @return None.
+*
+* @note
+*
+* void XHwIcap_mSetBram(u32 BaseAddress, u32 Offset, u32 Data);
+*
+*****************************************************************************/
+#define XHwIcap_mSetBram(BaseAddress, Offset, Data) \
+ ( XIo_Out32((BaseAddress+(Offset<<2)), (Data)) )
+
+
+#endif /* end of protection macro */
Index: drivers/misc/xilinx_hwicap/xhwicap_set_configuration.c
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_set_configuration.c (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_set_configuration.c (revision 486)
@@ -0,0 +1,130 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_set_configuration.c,v 1.2 2003/12/10 00:03:53 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_set_configuration.c
+*
+* This file contains the function that loads a partial bitstream located
+* in system memory into the device (ICAP).
+*
+* @note none.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/20/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+#include "xhwicap_i.h"
+#include <xbasic_types.h>
+#include <xstatus.h>
+
+/************************** Constant Definitions ****************************/
+
+#define XHI_BUFFER_START 0
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Loads a partial bitstream from system memory.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Data - Address of the data representing the partial bitstream
+*
+* @param Size - the size of the partial bitstream in 32 bit words.
+*
+* @return XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_SetConfiguration(XHwIcap *InstancePtr, u32 *Data,
+ u32 Size)
+{
+ XStatus Status;
+ s32 BufferCount=0;
+ s32 NumWrites=0;
+ Xboolean Dirty=XFALSE;
+ s32 I;
+
+ /* Loop through all the data */
+ for (I=0,BufferCount=0;I<Size;I++)
+ {
+
+ /* Copy data to bram */
+ XHwIcap_StorageBufferWrite(InstancePtr, BufferCount, Data[I]);
+ Dirty=XTRUE;
+
+ if (BufferCount == XHI_MAX_BUFFER_INTS-1)
+ {
+ /* Write data to ICAP */
+ Status = XHwIcap_DeviceWrite(InstancePtr, XHI_BUFFER_START,
+ XHI_MAX_BUFFER_INTS);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ BufferCount=0;
+ NumWrites++;
+ Dirty=XFALSE;
+ } else
+ {
+ BufferCount++;
+ }
+ }
+
+ /* Write unwritten data to ICAP */
+ if (Dirty==XTRUE)
+ {
+ /* Write data to ICAP */
+ Status = XHwIcap_DeviceWrite(InstancePtr, XHI_BUFFER_START,
+ BufferCount+1);
+ if (Status == XST_SUCCESS)
+ {
+ return Status;
+ }
+ }
+ return XST_SUCCESS;
+};
+
Index: drivers/misc/xilinx_hwicap/xhwicap_device_write_frame.c
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_device_write_frame.c (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_device_write_frame.c (revision 486)
@@ -0,0 +1,196 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_device_write_frame.c,v 1.4 2003/12/10 00:03:53 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_device_write_frame.c
+*
+* This file contains the function that writes the frame stored in the
+* bram storage buffer to the device (ICAP).
+*
+* @note none.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/20/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+#include "xhwicap_i.h"
+#include <xbasic_types.h>
+#include <xstatus.h>
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Writes one frame from the storage buffer and puts it in the device
+* (ICAP).
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Block - Block Address (XHI_FAR_CLB_BLOCK,
+* XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+*
+* @param MajorFrame - selects the column
+*
+* @param MinorFrame - selects frame inside column
+*
+* @return XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, s32 Block,
+ s32 MajorFrame, s32 MinorFrame)
+{
+
+ s32 HeaderBytes;
+ s32 Packet;
+ s32 Data;
+ s32 TotalWords;
+ XStatus Status;
+
+
+ /* Make sure we aren't trying to write more than what we have room
+ * for. */
+ if (InstancePtr->BytesPerFrame >
+ (XHI_MAX_BUFFER_BYTES-XHI_HEADER_BUFFER_BYTES))
+ {
+ return XST_BUFFER_TOO_SMALL;
+ }
+
+ /* DUMMY and SYNC */
+ XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
+
+ /* Reset CRC */
+ Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+ Data = XHI_CMD_RCRC;
+ XHwIcap_StorageBufferWrite(InstancePtr, 2,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 3,Data);
+
+ /* ID register */
+ Packet = XHwIcap_Type1Write(XHI_IDCODE) | 1;
+ Data = InstancePtr->DeviceIdCode;
+ XHwIcap_StorageBufferWrite(InstancePtr, 4,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 5,Data);
+
+ /* Bypass CRC */
+ Packet = XHwIcap_Type1Write(XHI_COR) | 1;
+ Data = 0x20053FE5;
+ XHwIcap_StorageBufferWrite(InstancePtr, 6,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 7,Data);
+
+ /* Setup CMD register */
+ Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+ Data = XHI_CMD_WCFG;
+ XHwIcap_StorageBufferWrite(InstancePtr, 8,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 9,Data);
+
+ /* Setup FAR */
+ Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
+ Data = XHwIcap_SetupFar(Block, MajorFrame, MinorFrame);
+ XHwIcap_StorageBufferWrite(InstancePtr, 10,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 11,Data);
+
+ /* Setup Packet header. */
+ TotalWords = InstancePtr->WordsPerFrame << 1; /* mult by 2 */
+ if (TotalWords < XHI_TYPE_1_PACKET_MAX_WORDS)
+ {
+ /* Create Type 1 Packet. */
+ Packet = XHwIcap_Type1Write(XHI_FDRI) | TotalWords;
+ XHwIcap_StorageBufferWrite(InstancePtr, 12,Packet);
+
+ HeaderBytes = 52; /* 13*4 */
+ }
+ else
+ {
+ /* Create Type 2 Packet. */
+ Packet = XHwIcap_Type1Write(XHI_FDRI);
+ XHwIcap_StorageBufferWrite(InstancePtr, 12,Packet);
+
+ Packet = XHI_TYPE_2_WRITE | TotalWords;
+ XHwIcap_StorageBufferWrite(InstancePtr, 13,Packet);
+
+ HeaderBytes = 56; /* 14*4 */
+ }
+
+ /* append auto CRC word. */
+ XHwIcap_StorageBufferWrite(InstancePtr, (XHI_HEADER_BUFFER_WORDS+
+ InstancePtr->WordsPerFrame), XHI_DISABLED_AUTO_CRC);
+
+ /* Write out Header. Div by 4 for words*/
+ Status = XHwIcap_DeviceWrite(InstancePtr, 0, (HeaderBytes>>2));
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* Write out data. */
+ Status = XHwIcap_DeviceWrite(InstancePtr, XHI_HEADER_BUFFER_WORDS,
+ InstancePtr->WordsPerFrame);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* Write out pad frame. */
+ Status = XHwIcap_DeviceWrite(InstancePtr, XHI_HEADER_BUFFER_WORDS,
+ InstancePtr->WordsPerFrame + 1);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* send DESYNC command */
+ Status = XHwIcap_CommandDesync(InstancePtr);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ return XST_SUCCESS;
+};
+
Index: drivers/misc/xilinx_hwicap/xhwicap_device_read_frame.c
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_device_read_frame.c (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_device_read_frame.c (revision 486)
@@ -0,0 +1,157 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_device_read_frame.c,v 1.3 2003/12/10 00:03:53 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_device_read_frame.c
+*
+* This file contains the function that reads a specified frame from the
+* device (ICAP) and stores it in the bram storage buffer.
+*
+* @note none.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/20/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap.h"
+#include "xhwicap_i.h"
+#include <xbasic_types.h>
+#include <xstatus.h>
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Reads one frame from the device and puts it in the storage buffer.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Block - Block Address (XHI_FAR_CLB_BLOCK,
+* XHI_FAR_BRAM_BLOCK, XHI_FAR_BRAM_INT_BLOCK)
+*
+* @param MajorFrame - selects the column
+*
+* @param MinorFrame - selects frame inside column
+*
+* @return XST_SUCCESS, XST_BUFFER_TOO_SMALL or XST_INVALID_PARAM.
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, s32 Block,
+ s32 MajorFrame, s32 MinorFrame)
+{
+
+ s32 Packet;
+ s32 Data;
+ s32 TotalWords;
+ XStatus Status;
+
+ /* Make sure we aren't trying to read more than what we have room
+ * for. */
+ if (InstancePtr->BytesPerFrame >
+ (XHI_MAX_BUFFER_BYTES-XHI_HEADER_BUFFER_BYTES))
+ {
+ return XST_BUFFER_TOO_SMALL;
+ }
+
+ /* DUMMY and SYNC */
+ XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
+
+ /* Setup CMD register to read configuration */
+ Packet = XHwIcap_Type1Write(XHI_CMD) | 1;
+ Data = XHI_CMD_RCFG;
+ XHwIcap_StorageBufferWrite(InstancePtr, 2,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 3,Data);
+
+ /* Setup FAR register. */
+ Packet = XHwIcap_Type1Write(XHI_FAR) | 1;
+ Data = XHwIcap_SetupFar(Block, MajorFrame, MinorFrame);
+ XHwIcap_StorageBufferWrite(InstancePtr, 4,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 5,Data);
+
+ /* Setup read data packet header. */
+ TotalWords = InstancePtr->WordsPerFrame << 1; /* mult by 2 */
+
+ /* Create Type one packet */
+ Packet = XHwIcap_Type1Read(XHI_FDRO) | TotalWords;
+ XHwIcap_StorageBufferWrite(InstancePtr, 6,Packet);
+ XHwIcap_StorageBufferWrite(InstancePtr, 7,0); /* flush */
+ XHwIcap_StorageBufferWrite(InstancePtr, 8,0); /* flush */
+
+ /* Write To ICAP. */
+ Status = XHwIcap_DeviceWrite(InstancePtr, 0, 9);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* Read pad frame (skip header). */
+ Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS,
+ InstancePtr->WordsPerFrame);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* Read data on top of pad frame (skip header). */
+ Status = XHwIcap_DeviceRead(InstancePtr, XHI_HEADER_BUFFER_WORDS,
+ InstancePtr->WordsPerFrame);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ /* send DESYNC command */
+ Status = XHwIcap_CommandDesync(InstancePtr);
+ if (Status != XST_SUCCESS)
+ {
+ return Status;
+ }
+
+ return XST_SUCCESS;
+};
+
Index: drivers/misc/xilinx_hwicap/xhwicap_srp.c
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_srp.c (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_srp.c (revision 486)
@@ -0,0 +1,589 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_srp.c,v 1.6 2003/12/10 00:40:05 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_srp.c
+*
+* This file contains SRP (self reconfigurable platform) driver
+* functions.
+*
+* The SRP contains functions that allow low level access to
+* configuration memory through the ICAP port. This API provide methods
+* for reading and writing data, frames, and partial bitstreams to the
+* ICAP port.
+*
+* @note
+*
+* Only Virtex 2 and Virtex 2 Pro devices are supported as they are the
+* only devices that contain the VIRTEX2_ICAP component.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/17/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include <asm/xparameters.h>
+#include <xbasic_types.h>
+#include <xstatus.h>
+#include "xhwicap_i.h"
+#include "xhwicap.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Initialize a XHwIcap instance..
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param BaseAddress - Base Address of the instance of this
+* component.
+*
+* @param DeviceId - User defined ID for the instance of this
+* component.
+*
+* @param DeviceIdCode - IDCODE of the FPGA device.
+*
+* @return XST_SUCCESS or XST_INVALID_PARAM.
+*
+* @note Virtex2/Pro devices only have one ICAP port so there should
+* only be one opb_hwicap instantiated (per FPGA) in a system.
+*
+*****************************************************************************/
+XStatus XHwIcap_Initialize(XHwIcap *InstancePtr, u16 DeviceId,
+ u32 DeviceIdCode)
+{
+ XHwIcap_Config *HwIcapConfigPtr;
+ u32 Rows;
+ u32 Cols;
+ u32 BramCols;
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+
+ /*
+ * If the device is ready, disallow the initialize and return a status
+ * indicating it is started. This allows the user to stop the device
+ * and reinitialize, but prevents a user from inadvertently initializing.
+ */
+
+ if (InstancePtr->IsReady == XCOMPONENT_IS_READY)
+ {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /* Default value until component is ready */
+ InstancePtr->IsReady = 0;
+
+ /*
+ * Lookup the device configuration in the configuration table. Use this
+ * configuration info when initializing this component.
+ */
+ HwIcapConfigPtr = XHwIcap_LookupConfig(DeviceId);
+
+ if (HwIcapConfigPtr == (XHwIcap_Config *)XNULL)
+ {
+ return XST_DEVICE_NOT_FOUND;
+ }
+
+
+ switch (DeviceIdCode)
+ {
+ case XHI_XC2V40:
+ Rows = 8;
+ Cols = 8;
+ BramCols = 2;
+ break;
+ case XHI_XC2V80:
+ Rows = 16;
+ Cols = 8;
+ BramCols = 2;
+ break;
+ case XHI_XC2V250:
+ Rows = 24;
+ Cols = 16;
+ BramCols = 4;
+ break;
+ case XHI_XC2V500:
+ Rows = 32;
+ Cols = 24;
+ BramCols = 4;
+ break;
+ case XHI_XC2V1000:
+ Rows = 40;
+ Cols = 32;
+ BramCols = 4;
+ break;
+ case XHI_XC2V1500:
+ Rows = 48;
+ Cols = 40;
+ BramCols = 4;
+ break;
+ case XHI_XC2V2000:
+ Rows = 56;
+ Cols = 48;
+ BramCols = 4;
+ break;
+ case XHI_XC2V3000:
+ Rows = 64;
+ Cols = 56;
+ BramCols = 6;
+ break;
+ case XHI_XC2V4000:
+ Rows = 80;
+ Cols = 72;
+ BramCols = 6;
+ break;
+ case XHI_XC2V6000:
+ Rows = 96;
+ Cols = 88;
+ BramCols = 6;
+ break;
+ case XHI_XC2V8000:
+ Rows = 112;
+ Cols = 104;
+ BramCols = 6;
+ break;
+ case XHI_XC2VP2:
+ Rows = 16;
+ Cols = 22;
+ BramCols = 4;
+ break;
+ case XHI_XC2VP4:
+ Rows = 40;
+ Cols = 22;
+ BramCols = 4;
+ break;
+ case XHI_XC2VP7:
+ Rows = 40;
+ Cols = 34;
+ BramCols = 6;
+ break;
+ case XHI_XC2VP20:
+ Rows = 56;
+ Cols = 46;
+ BramCols = 8;
+ break;
+ case XHI_XC2VP30:
+ Rows = 80;
+ Cols = 46;
+ BramCols = 8;
+ break;
+ case XHI_XC2VP40:
+ Rows = 88;
+ Cols = 58;
+ BramCols = 10;
+ break;
+ case XHI_XC2VP50:
+ Rows = 88;
+ Cols = 70;
+ BramCols = 12;
+ break;
+ case XHI_XC2VP70:
+ Rows = 104;
+ Cols = 82;
+ BramCols = 14;
+ break;
+ case XHI_XC2VP100:
+ Rows = 120;
+ Cols = 94;
+ BramCols = 16;
+ break;
+ case XHI_XC2VP125:
+ Rows = 136;
+ Cols = 106;
+ BramCols = 18;
+ break;
+ default :
+ return XST_INVALID_PARAM;
+ break;
+ }
+
+ InstancePtr->BaseAddress = HwIcapConfigPtr->BaseAddress;
+ InstancePtr->DeviceId = DeviceId;
+ InstancePtr->DeviceIdCode = DeviceIdCode;
+
+ InstancePtr->Rows = Rows;
+ InstancePtr->Cols = Cols;
+ InstancePtr->BramCols = BramCols;
+
+ InstancePtr->BytesPerFrame = ((96*2+80*Rows)/8);
+ InstancePtr->WordsPerFrame = (InstancePtr->BytesPerFrame/4);
+ InstancePtr->ClbBlockFrames = (4 +22*2 + 4*2 + 22*Cols);
+ InstancePtr->BramBlockFrames = (64*BramCols);
+ InstancePtr->BramIntBlockFrames = (22*BramCols);
+
+ InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+} /* end XHwIcap_Initialize() */
+
+/****************************************************************************/
+/**
+*
+* Stores data in the storage buffer at the specified address.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Address - bram word address
+*
+* @param Data - data to be stored at address
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XHwIcap_StorageBufferWrite(XHwIcap *InstancePtr, u32 Address,
+ u32 Data)
+{
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_VOID(InstancePtr != XNULL);
+ XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* Check range of address. */
+ XASSERT_VOID(Address<XHI_MAX_BUFFER_INTS);
+
+ /* Write data to storage buffer. */
+ XHwIcap_mSetBram(InstancePtr->BaseAddress, Address, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* Read data from the specified address in the storage buffer..
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Address - bram word address
+*
+* @return Data.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XHwIcap_StorageBufferRead(XHwIcap *InstancePtr, u32 Address)
+{
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* Check range of address. */
+ XASSERT_NONVOID(Address<XHI_MAX_BUFFER_INTS);
+
+ /* Read data from address. Multiply Address by 4 since 4 bytes per
+ * word.*/
+ return XHwIcap_mGetBram(InstancePtr->BaseAddress, Address);
+}
+
+/****************************************************************************/
+/**
+*
+* Reads bytes from the device (ICAP) and puts it in the storage buffer.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Offset - The storage buffer start address.
+*
+* @param NumInts - The number of words (32 bit) to read from the
+* device (ICAP).
+*
+*@return XStatus - XST_SUCCESS or XST_DEVICE_BUSY or XST_INVALID_PARAM
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_DeviceRead(XHwIcap *InstancePtr, u32 Offset,
+ u32 NumInts)
+
+{
+
+ s32 Retries = 0;
+
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* Check range of address. */
+ XASSERT_NONVOID((Offset+NumInts)<XHI_MAX_BUFFER_INTS);
+
+ if ((Offset+NumInts)<XHI_MAX_BUFFER_INTS)
+ {
+ /* setSize NumInts*4 to get bytes. */
+ XHwIcap_mSetSizeReg((InstancePtr->BaseAddress),(NumInts<<2));
+ XHwIcap_mSetOffsetReg((InstancePtr->BaseAddress), Offset);
+ XHwIcap_mSetRncReg((InstancePtr->BaseAddress), XHI_READBACK);
+
+ while (XHwIcap_mGetDoneReg(InstancePtr->BaseAddress)==XHI_NOT_FINISHED)
+ {
+ Retries++;
+ if (Retries > XHI_MAX_RETRIES)
+ {
+ return XST_DEVICE_BUSY;
+ }
+ }
+ } else
+ {
+ return XST_INVALID_PARAM;
+ }
+ return XST_SUCCESS;
+
+};
+
+
+/****************************************************************************/
+/**
+*
+* Writes bytes from the storage buffer and puts it in the device (ICAP).
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Offset - The storage buffer start address.
+*
+* @param NumInts - The number of words (32 bit) to read from the
+* device (ICAP).
+*
+*@return XStatus - XST_SUCCESS or XST_DEVICE_BUSY or XST_INVALID_PARAM
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u32 Offset,
+ u32 NumInts)
+{
+
+ s32 Retries = 0;
+
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* Check range of address. */
+ XASSERT_NONVOID((Offset+NumInts)<XHI_MAX_BUFFER_INTS);
+
+ if ((Offset+NumInts)<XHI_MAX_BUFFER_INTS)
+ {
+ XHwIcap_mSetSizeReg((InstancePtr->BaseAddress),NumInts<<2);
+ XHwIcap_mSetOffsetReg((InstancePtr->BaseAddress), Offset);
+ XHwIcap_mSetRncReg((InstancePtr->BaseAddress), XHI_CONFIGURE);
+
+ while (XHwIcap_mGetDoneReg(InstancePtr->BaseAddress)==XHI_NOT_FINISHED)
+ {
+ Retries++;
+ if (Retries > XHI_MAX_RETRIES)
+ {
+ return XST_DEVICE_BUSY;
+ }
+ }
+ } else
+ {
+ return XST_INVALID_PARAM;
+ }
+ return XST_SUCCESS;
+
+};
+
+XStatus XHwIcap_DeviceWriteBytes(XHwIcap *InstancePtr, u32 Offset,
+ u32 NumBytes)
+{
+
+ s32 Retries = 0;
+
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* Check range of address. */
+ XASSERT_NONVOID((Offset+NumBytes)<XHI_MAX_BUFFER_BYTES);
+
+ if ((Offset+NumBytes)<XHI_MAX_BUFFER_BYTES)
+ {
+ XHwIcap_mSetSizeReg((InstancePtr->BaseAddress), NumBytes);
+ XHwIcap_mSetOffsetReg((InstancePtr->BaseAddress), Offset);
+ XHwIcap_mSetRncReg((InstancePtr->BaseAddress), XHI_CONFIGURE);
+
+ while (XHwIcap_mGetDoneReg(InstancePtr->BaseAddress)==XHI_NOT_FINISHED)
+ {
+ Retries++;
+ if (Retries > XHI_MAX_RETRIES)
+ {
+ return XST_DEVICE_BUSY;
+ }
+ }
+ } else
+ {
+ return XST_INVALID_PARAM;
+ }
+ return XST_SUCCESS;
+
+};
+
+
+/****************************************************************************/
+/**
+*
+* Sends a DESYNC command to the ICAP port.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+*@return XStatus - XST_SUCCESS or XST_DEVICE_BUSY or XST_INVALID_PARAM
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_CommandDesync(XHwIcap *InstancePtr)
+{
+ XStatus Status;
+
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ XHwIcap_StorageBufferWrite(InstancePtr, 0,
+ (XHwIcap_Type1Write(XHI_CMD) | 1));
+ XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_CMD_DESYNCH);
+ XHwIcap_StorageBufferWrite(InstancePtr, 2, XHI_DUMMY_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_DUMMY_PACKET);
+ Status = XHwIcap_DeviceWrite(InstancePtr, 0, 4); /* send four words */
+
+ XASSERT_NONVOID(Status == XST_SUCCESS);
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Sends a CAPTURE command to the ICAP port. This command caputres all
+* of the flip flop states so they will be available during readback.
+* One can use this command instead of enabling the CAPTURE block in the
+* design.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @return XStatus - XST_SUCCESS or XST_DEVICE_BUSY or XST_INVALID_PARAM
+*
+* @note None.
+*
+*****************************************************************************/
+XStatus XHwIcap_CommandCapture(XHwIcap *InstancePtr)
+{
+ XStatus Status;
+
+ /*
+ * Assert validates the input arguments
+ */
+ XASSERT_NONVOID(InstancePtr != XNULL);
+ XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+ /* DUMMY and SYNC */
+ XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 2,
+ (XHwIcap_Type1Write(XHI_CMD) | 1));
+ XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_CMD_GCAPTURE);
+ XHwIcap_StorageBufferWrite(InstancePtr, 4, XHI_DUMMY_PACKET);
+ XHwIcap_StorageBufferWrite(InstancePtr, 5, XHI_DUMMY_PACKET);
+ Status = XHwIcap_DeviceWrite(InstancePtr, 0, 6); /* send six words */
+
+ XASSERT_NONVOID(Status == XST_SUCCESS);
+
+ return Status;
+}
+
+/****************************************************************************
+*
+* Looks up the device configuration based on the unique device ID. The table
+* HwIcapConfigTable contains the configuration info for each device in the
+* system.
+*
+* @param DeviceId is the unique device ID to match on.
+*
+* @return
+*
+* A pointer to the configuration data for the device, or XNULL if no match
+* was found.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XHwIcap_Config *XHwIcap_LookupConfig(u16 DeviceId)
+{
+ XHwIcap_Config *CfgPtr = XNULL;
+ int i;
+
+ for (i=0; i < CONFIG_XILINX_HWICAP_NUM_INSTANCES; i++)
+ {
+ if (XHwIcap_ConfigTable[i].DeviceId == DeviceId)
+ {
+ CfgPtr = &XHwIcap_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+
+
+
+
+
Index: drivers/misc/xilinx_hwicap/xhwicap.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap.h (revision 486)
@@ -0,0 +1,265 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap.h,v 1.9 2004/01/07 01:23:21 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap.h
+*
+* This file contains the software API definition of the Xilinx Hardware
+* ICAP (hwicap) component.
+*
+* The Xilinx Hardware ICAP controller is designed to allow
+* reconfiguration of select FPGA resources as well as loading partial
+* bitstreams from system memory through the Internal Configuration
+* Access Port (ICAP).
+*
+* The source code for the XHwIcap_SetClbBits and XHwIcap_GetClbBits
+* functions are not included. These functions are delivered as .o
+* files. Libgen uses the appropriate .o files for the target processor.
+* This is specified by the hwicap_v2_1_0.tcl file in the data directory.
+*
+* @note
+*
+* There are a few items to be aware of when using this driver. 1) Only
+* Virtex 2 and Virtex 2 Pro devices are supported as they are the only
+* devices that contain the ICAP_VIRTEX2 component. 2) The ICAP port is
+* disabled when the configuration mode, via the MODE pins, is set to
+* Boundary Scan/JTAG. The ICAP is enabled in all other configuration
+* modes and it is possible to configure the device via JTAG in all
+* configuration modes. 3) Reading or writing to columns containing
+* SRL16's or LUT RAM's can cause corruption of data in those elements.
+* Avoid reading or writing to columns containing SRL16's or LUT RAM's.
+*
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver Who Date Changes ----- ---- --------
+* ------------------------------------------------------- 1.00a bjb
+* 11/17/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_H_ /* prevent circular inclusions */
+#define XHWICAP_H_ /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xhwicap_l.h"
+#include <xstatus.h>
+
+/************************** Constant Definitions ****************************/
+
+/* Virtex 2 Device constants. The IDCODE for this device. */
+#define XHI_XC2V40 0x01008093UL
+#define XHI_XC2V80 0x01010093UL
+#define XHI_XC2V250 0x01018093UL
+#define XHI_XC2V500 0x01020093UL
+#define XHI_XC2V1000 0x01028093UL
+#define XHI_XC2V1500 0x01030093UL
+#define XHI_XC2V2000 0x01038093UL
+#define XHI_XC2V3000 0x01040093UL
+#define XHI_XC2V4000 0x01050093UL
+#define XHI_XC2V6000 0x01060093UL
+#define XHI_XC2V8000 0x01070093UL
+
+/* Virtex2 Pro Device constants. The IDCODE for this device. */
+#define XHI_XC2VP2 0x01226093UL
+#define XHI_XC2VP4 0x0123E093UL
+#define XHI_XC2VP7 0x0124A093UL
+#define XHI_XC2VP20 0x01266093UL
+#define XHI_XC2VP30 0x0127E093UL
+#define XHI_XC2VP40 0x01292093UL
+#define XHI_XC2VP50 0x0129E093UL
+#define XHI_XC2VP70 0x012BA093UL
+#define XHI_XC2VP100 0x012D6093UL
+#define XHI_XC2VP125 0x012F2093UL
+
+/* ERROR Codes - if needed */
+
+/************************** Type Definitions ********************************/
+
+/**
+* This typedef contains configuration information for the device.
+*/
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Register base address */
+
+} XHwIcap_Config;
+
+/**
+* The XHwIcap driver instance data. The user is required to allocated a
+* variable of this type for every opb_hwicap device in the system. A
+* pointer to a variable of this type is then passed to the driver API
+* functions.
+*
+* Note - Virtex2/Pro devices only have one ICAP port so there should
+* be at most only one opb_hwicap instantiated (per FPGA) in a system.
+*/
+typedef struct
+{
+ u32 BaseAddress; /* Base address of this component */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 DeviceIdCode; /* IDCODE of targeted device */
+ u16 DeviceId; /* User assigned ID for this component */
+ u32 Rows; /* Number of CLB rows */
+ u32 Cols; /* Number of CLB cols */
+ u32 BramCols; /* Number of BRAM cols */
+ u32 BytesPerFrame; /* Number of Bytes per minor Frame */
+ u32 WordsPerFrame; /* Number of Words per minor Frame */
+ u32 ClbBlockFrames; /* Number of CLB type minor Frames */
+ u32 BramBlockFrames; /* Number of Bram type minor Frames */
+ u32 BramIntBlockFrames; /* Number of BramInt type minor Frames */
+} XHwIcap;
+
+
+
+
+/***************** Macro (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceX coordinate to a column coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param X - the SliceX coordinate to be converted
+*
+* @return Column
+*
+* @note
+*
+* u32 XHwIcap_mSliceX2Col(u32 X);
+*
+*****************************************************************************/
+#define XHwIcap_mSliceX2Col(X) \
+ ( (X >> 1) + 1)
+
+/****************************************************************************/
+/**
+*
+* Converts a CLB SliceY coordinate to a row coordinate used by the
+* XHwIcap_GetClbBits and XHwIcap_SetClbBits functions.
+*
+* @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
+*
+* @param Y - the SliceY coordinate to be converted
+*
+* @return Row
+*
+* @note
+*
+* u32 XHwIcap_mSliceY2Row(XHwIcap *InstancePtr, u32 Y);
+*
+*****************************************************************************/
+#define XHwIcap_mSliceY2Row(InstancePtr, Y) \
+ ( (InstancePtr)->Rows - (Y >> 1) )
+
+/****************************************************************************/
+/**
+*
+* Figures out which slice in a CLB is targeted by a given
+* (SliceX,SliceY) pair. This slice value is used for indexing in
+* resource arrays.
+*
+* @param X - the SliceX coordinate to be converted
+*
+* @param Y - the SliceY coordinate to be converted
+*
+* @return Slice index
+*
+* @note
+*
+* u32 XHwIcap_mSliceXY2Slice(u32 X, u32 Y);
+*
+*****************************************************************************/
+#define XHwIcap_mSliceXY2Slice(X,Y) \
+ ( ((X % 2) << 1) + (Y % 2) )
+
+
+/************************** Function Prototypes *****************************/
+
+
+/* These functions are the ones defined in the lower level
+ * Self-Reconfiguration Platform (SRP) API.
+ */
+
+/* Initializes a XHwIcap instance.. */
+XStatus XHwIcap_Initialize(XHwIcap *InstancePtr, u16 DeviceId,
+ u32 DeviceIdCode);
+
+/* Reads integers from the device into the storage buffer. */
+XStatus XHwIcap_DeviceRead(XHwIcap *InstancePtr, u32 Offset,
+ u32 NumInts);
+
+/* Writes integers to the device from the storage buffer. */
+XStatus XHwIcap_DeviceWrite(XHwIcap *InstancePtr, u32 Offset,
+ u32 NumInts);
+
+/* Writes bytes to the device from the storage buffer. */
+XStatus XHwIcap_DeviceWriteBytes(XHwIcap *InstancePtr, u32 Offset,
+ u32 Numbytes);
+
+/* Writes word to the storage buffer. */
+void XHwIcap_StorageBufferWrite(XHwIcap *InstancePtr, u32 Address,
+ u32 Data);
+
+/* Reads word from the storage buffer. */
+u32 XHwIcap_StorageBufferRead(XHwIcap *InstancePtr, u32 Address);
+
+/* Reads one frame from the device and puts it in the storage buffer. */
+XStatus XHwIcap_DeviceReadFrame(XHwIcap *InstancePtr, s32 Block,
+ s32 MajorFrame, s32 MinorFrame);
+
+/* Writes one frame from the storage buffer and puts it in the device. */
+XStatus XHwIcap_DeviceWriteFrame(XHwIcap *InstancePtr, s32 Block,
+ s32 MajorFrame, s32 MinorFrame);
+
+/* Loads a partial bitstream from system memory. */
+XStatus XHwIcap_SetConfiguration(XHwIcap *InstancePtr, u32 *Data,
+ u32 Size);
+
+/* Sends a DESYNC command to the ICAP */
+XStatus XHwIcap_CommandDesync(XHwIcap *InstancePtr);
+
+/* Sends a CAPTURE command to the ICAP */
+XStatus XHwIcap_CommandCapture(XHwIcap *InstancePtr);
+
+/* Reconfigures the specified resource to the specified value. */
+XStatus XHwIcap_SetClbBits(XHwIcap *InstancePtr, s32 Row, s32 Col,
+ const u8 Resource[][2], const u8 Value[], s32 NumBits);
+
+/* Reads the current configuration of the specified resource. */
+XStatus XHwIcap_GetClbBits(XHwIcap *InstancePtr, s32 Row, s32 Col,
+ const u8 Resource[][2], u8 Value[], s32 NumBits);
+
+/* Pointer to a function that returns XHwIcap_Config info. */
+XHwIcap_Config *XHwIcap_LookupConfig(u16 DeviceId);
+
+
+/************************** Variable Declarations ***************************/
+
+
+#endif
Index: drivers/misc/xilinx_hwicap/xhwicap_clb_srinv.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_clb_srinv.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_clb_srinv.h (revision 486)
@@ -0,0 +1,101 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_clb_srinv.h,v 1.5 2003/12/10 16:52:45 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
+* INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_srinv.h
+*
+* This header file contains bit information about the CLB SRINV resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/14/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_CLB_SRINV_H_ /* prevent circular inclusions */
+#define XHWICAP_CLB_SRINV_H_ /* by using protection macros */
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+typedef struct
+{
+ /* SRINV Resource values. */
+ const u8 SR_B[1]; /* Invert SR Line. */
+ const u8 SR[1]; /* Do not Invert SR line. */
+
+ /** Configure the SRINV mux (SR_B or SR). This array indexed by
+ * slice (0-3). */
+ const u8 RES[4][1][2];
+} XHwIcap_ClbSrinv;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/**
+* This structure defines the SRINV mux
+*/
+const XHwIcap_ClbSrinv XHI_CLB_SRINV =
+{
+ /* SR_B*/
+ {0},
+ /* SR*/
+ {1},
+ /* RES*/
+ {
+ /* Slice 0. */
+ {
+ {1, 4}
+ },
+ /* Slice 1. */
+ {
+ {16, 4}
+ },
+ /* Slice 2. */
+ {
+ {7, 4}
+ },
+ /* Slice 3. */
+ {
+ {10, 4}
+ }
+ },
+
+};
+
+#endif
Index: drivers/misc/xilinx_hwicap/xhwicap_g.c
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_g.c (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_g.c (revision 486)
@@ -0,0 +1,71 @@
+/* $Id: xhwicap_g.c,v 1.1 2003/12/10 00:02:17 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2002 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_g.c
+*
+* This file contains a configuration table that specifies the configuration of
+* opb_hwicap devices in the system. Each device in the system should have an
+* entry in the table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a bjb 12/08/03 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xhwicap.h"
+#include <asm/xparameters.h>
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Prototypes ******************************/
+
+/**
+ * The configuration table for opb_hwicap devices
+ */
+XHwIcap_Config XHwIcap_ConfigTable[CONFIG_XILINX_HWICAP_NUM_INSTANCES] =
+{
+ {
+ 0, /* Unique ID of device */
+ CONFIG_XILINX_HWICAP_0_BASEADDR, /* Device base address */
+ },
+};
+
+
Index: drivers/misc/xilinx_hwicap/Makefile
===================================================================
--- drivers/misc/xilinx_hwicap/Makefile (revision 0)
+++ drivers/misc/xilinx_hwicap/Makefile (revision 486)
@@ -0,0 +1,21 @@
+#
+# Makefile for Xilinx HWICAP driver
+#
+
+EXTRA_CFLAGS += -I$(TOPDIR)/arch/microblaze/xilinx_ocp
+
+# the uClinux adapter for the xilinx driver code
+xilinx_hwicap-objs += adapter.o
+
+# The Xilinx OS independent code
+xilinx_hwicap-objs += xhwicap_device_read_frame.o xhwicap_g.o \
+ xhwicap_srp.o xhwicap_device_write_frame.o \
+ xhwicap_set_configuration.o
+
+obj-$(CONFIG_XILINX_HWICAP) := xilinx_hwicap.o
+
+xilinx_hwicap.o: $(xilinx_hwicap-objs)
+ $(LD) -r -o $@ $(xilinx_hwicap-objs)
+
+include $(TOPDIR)/Rules.make
+
Index: drivers/misc/xilinx_hwicap/xhwicap_clb_lut.h
===================================================================
--- drivers/misc/xilinx_hwicap/xhwicap_clb_lut.h (revision 0)
+++ drivers/misc/xilinx_hwicap/xhwicap_clb_lut.h (revision 486)
@@ -0,0 +1,263 @@
+/* $Header: /devl/xcs/repo/env/Databases/ip2/processor/software/devel/hwicap/v1_00_a/src/xhwicap_clb_lut.h,v 1.4 2003/12/10 16:52:45 brandonb Exp $ */
+/*****************************************************************************
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
+* INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2003 Xilinx Inc.
+* All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xhwicap_clb_lut.h
+*
+* This header file contains bit information about the CLB LUT resource.
+* This header file can be used with the XHwIcap_GetClbBits() and
+* XHwIcap_SetClbBits() functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bjb 11/14/03 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XHWICAP_CLB_LUT_H_ /* prevent circular inclusions */
+#define XHWICAP_CLB_LUT_H_ /* by using protection macros */
+
+/************************** Constant Definitions ****************************/
+
+/** Index into SLICE and MODE for F LUT. */
+#define XHI_CLB_LUT_F 0
+/** Index into SLICE and MODE for G LUT. */
+#define XHI_CLB_LUT_G 1
+
+/**************************** Type Definitions ******************************/
+
+typedef struct
+{
+ /* MODE resource values. */
+ const u8 LUT_MODE[1]; /* Set MODE to LUT mode */
+ const u8 ROM_MODE[1]; /* Set MODE to ROM mode. (Same as LUT mode) */
+ const u8 RAM_MODE[1]; /* Set MODE to RAM mode. */
+
+
+ /* CONFIG resource values. */
+ const u8 SHIFT_CONFIG[2]; /* Set CONFIG to shfiter. */
+ const u8 RAM_CONFIG[2]; /* Set CONFIG to ram. */
+ const u8 LUT_CONFIG[2]; /* Set CONFIG to LUT. */
+
+ /* RAM_MODE, ROM_MODE, or LUT_MODE. Indexed by the slice (0-3). If
+ * only one LUT is in RAM or SHIFT mode, it MUST be the G LUT.
+ */
+ const u8 MODE[4][1][2];
+
+ /* SHIFT_CONFIG, RAM_CONFIG, or LUT_CONFIG. Indexed by the slice
+ * (0-3). And then indexed by the logic element (LUT.F or LUT.G).
+ * Note that if the F LUT is in any sort of ram or shifter modes,
+ * the G LUT must also be in ram or shifter mode. Also, be sure to
+ * set the MODE bit appropriately. */
+ const u8 CONFIG[4][2][2][2];
+
+ /* LUT memory contents. Indexed by slice first (0-3) and by
+ * XHI_CLB_LUT_F or XHI_CLB_LUT_G second. **/
+ const u8 CONTENTS[4][2][16][2];
+
+} XHwIcap_ClbLut;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+* This structure defines the Look Up Tables, or <em>LUTs</em>.
+* in the Virtex2/Pro CLB. Note that there are 8 16-bit
+* LUTs, the F and G LUTs in Slice 0, 1, 2 and 3. These
+* LUTs can take any arbitrary bit pattern.
+*
+* <p>
+*
+* Note, that DUAL_PORT mode cannot be configured here. Thats because
+* it is essentially always in effect. But, it can only be used in the top
+* two slices (2 and 3) using the address lines from the bottom
+* two slices (0 and 1) for the write address. Although you can technically
+* put the bottom two slice LUTs in dual port mode in the fpga_editor,
+* the read and write addresses will always be the same. This is
+* different from the Virtex where the two LUTs in a slice were
+* combined to make a dual port RAM. In Virtex 2, every LUT is
+* dual ported, but only the top two have different read/write
+* addresses.
+*
+***************************************************************************/
+const XHwIcap_ClbLut XHI_CLB_LUT =
+{
+ /* LUT_MODE*/
+ {0},
+ /* ROM_MODE*/
+ {0},
+ /* RAM_MODE*/
+ {1},
+ /* SHIFT_CONFIG*/
+ {0,1},
+ /* RAM_CONFIG*/
+ {1,0},
+ /* LUT_CONFIG*/
+ {0,0},
+ /* MODE*/
+ {
+ /* Slice 0. */
+ {
+ {22, 1}
+ },
+ /* Slice 1. */
+ {
+ {62, 1}
+ },
+ /* Slice 2. */
+ {
+ {22, 2}
+ },
+ /* Slice 3. */
+ {
+ {62, 2}
+ }
+ },
+ /* CONFIG*/
+ {
+ /* Slice 0. */
+ {
+ /* LE 0. */
+ {
+ {18, 1}, {16, 1}
+ },
+ /* LE 1. */
+ {
+ {20, 1}, {21, 1}
+ }
+ },
+ /* Slice 1. */
+ {
+ /* LE 0. */
+ {
+ {58, 1}, {56, 1}
+ },
+ /* LE 1. */
+ {
+ {60, 1}, {61, 1}
+ }
+ },
+ /* Slice 2. */
+ {
+ /* LE 0. */
+ {
+ {18, 2}, {16, 2}
+ },
+ /* LE 1. */
+ {
+ {20, 2}, {21, 2}
+ }
+ },
+ /* Slice 3. */
+ {
+ /* LE 0. */
+ {
+ {58, 2}, {56, 2}
+ },
+ /* LE 1. */
+ {
+ {60, 2}, {61, 2}
+ }
+ }
+ },
+ /* CONTENTS*/
+ {
+ /* Slice 0. */
+ {
+ /* LE 0. */
+ {
+ {15, 1}, {14, 1}, {13, 1}, {12, 1}, {11, 1}, {10, 1},
+ {9, 1}, {8, 1}, {7, 1}, {6, 1}, {5, 1}, {4, 1},
+ {3, 1}, {2, 1}, {1, 1}, {0, 1}
+ },
+ /* LE 1. */
+ {
+ {24, 1}, {25, 1}, {26, 1}, {27, 1}, {28, 1}, {29, 1},
+ {30, 1}, {31, 1}, {32, 1}, {33, 1}, {34, 1}, {35, 1},
+ {36, 1}, {37, 1}, {38, 1}, {39, 1}
+ }
+ },
+ /* Slice 1. */
+ {
+ /* LE 0. */
+ {
+ {55, 1}, {54, 1}, {53, 1}, {52, 1}, {51, 1}, {50, 1},
+ {49, 1}, {48, 1}, {47, 1}, {46, 1}, {45, 1}, {44, 1},
+ {43, 1}, {42, 1}, {41, 1}, {40, 1}
+ },
+ /* LE 1. */
+ {
+ {64, 1}, {65, 1}, {66, 1}, {67, 1}, {68, 1}, {69, 1},
+ {70, 1}, {71, 1}, {72, 1}, {73, 1}, {74, 1}, {75, 1},
+ {76, 1}, {77, 1}, {78, 1}, {79, 1}
+ }
+ },
+ /* Slice 2. */
+ {
+ /* LE 0. */
+ {
+ {15, 2}, {14, 2}, {13, 2}, {12, 2}, {11, 2}, {10, 2},
+ {9, 2}, {8, 2}, {7, 2}, {6, 2}, {5, 2}, {4, 2},
+ {3, 2}, {2, 2}, {1, 2}, {0, 2}
+ },
+ /* LE 1. */
+ {
+ {24, 2}, {25, 2}, {26, 2}, {27, 2}, {28, 2}, {29, 2},
+ {30, 2}, {31, 2}, {32, 2}, {33, 2}, {34, 2}, {35, 2},
+ {36, 2}, {37, 2}, {38, 2}, {39, 2}
+ }
+ },
+ /* Slice 3. */
+ {
+ /* LE 0. */
+ {
+ {55, 2}, {54, 2}, {53, 2}, {52, 2}, {51, 2}, {50, 2},
+ {49, 2}, {48, 2}, {47, 2}, {46, 2}, {45, 2}, {44, 2},
+ {43, 2}, {42, 2}, {41, 2}, {40, 2}
+ },
+ /* LE 1. */
+ {
+ {64, 2}, {65, 2}, {66, 2}, {67, 2}, {68, 2}, {69, 2},
+ {70, 2}, {71, 2}, {72, 2}, {73, 2}, {74, 2}, {75, 2},
+ {76, 2}, {77, 2}, {78, 2}, {79, 2}
+ }
+ }
+ },
+
+};
+
+
+#endif
Index: drivers/misc/Config.in
===================================================================
--- drivers/misc/Config.in (revision 478)
+++ drivers/misc/Config.in (revision 486)
@@ -21,4 +21,8 @@
fi
+if [ "$CONFIG_MICROBLAZE" = "y" ]; then
+ tristate 'Xilinx ICAP driver' CONFIG_XILINX_HWICAP
+fi
+
endmenu
Index: drivers/misc/Makefile
===================================================================
--- drivers/misc/Makefile (revision 478)
+++ drivers/misc/Makefile (revision 486)
@@ -16,6 +16,10 @@
subdir-$(CONFIG_MICROBLAZE_FSLFIFO) += fslfifo
obj-$(CONFIG_MICROBLAZE_FSLFIFO) += fslfifo/fslfifo.o
+mod-subdirs += xilinx_hwicap
+subdir-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap
+obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/xilinx_hwicap.o
+
include $(TOPDIR)/Rules.make
fastdep: