Re: [partial-reconfig] Virtex-4 slice-based bus macros

["Zhi Guo" <guo.zhi@xxxxxxxxx>]

Hi Pete,

Thank you for your LUT-based BM!

I'm trying to implement the tutorial
on:http://elektronica.ehb.be/reco/PartialTutorial.htm onto a Virtex 4
(FX12) using LUT-based BM.

But I couldn't assembly. 
If I don't use the fake Gnd and Vcc, PAR gives me the following error:
FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.4:286 - A previous module
has placed the comp: capture/PWR_GND_0 on the same site: SLICE_X37Y81 where
the current guide comp PWR_VCC_0 also needs to be placed.  There exists at
least two guide files that contain logic 0/1 signals being driven from the
site location.   Process will terminate. ....

If I use the fake VCC and GND, PAR gives me the following error:
FATAL_ERROR:Guide:basgitaskphyspr.c:333:1.28.20.4:137 - Guide encountered a
   Logic0 or Logic1 signal GLOBAL_LOGIC1_6 that does not have a driver or
load within the module boundary. This problem may be caused by having a
constant driving the input from outside the module boundary or because a driver
or load comp did not meet the par-guiding criteria.  The design
will not be completely placed and routed by Par-Guide   Process
will terminate.......

It seems you are doing reconfiguration on Virtex 4. Do you have any
idea about this? Or maybe you could send out a tutorial about DPR on
Virtex 4. People would be moved to tears...

Thank you.

Zhi