Re: [partial-reconfig] problem during assembling of dynamic module - VirtexPro2

[Philipp Reinkemeier <partial-reconfig@xxxxxxxxxxxx>]

DPR DPR schrieb:
> My environment is
>  
> FPGA           - VirtexPro2
> Synthesis tool - XST
> Bus macro      - Original Xilinx Bus macro
> ISE Version    - 7.1i

Try it with ISE 6.X. I tried the modular design flow on ISE 7.1i4
with a design i made with ISE 6.3i3 and it did not work. But on the
older ISE version it work very well.

regards,
Philipp



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