Re: [partial-reconfig] DPR on Virtex4 - anyone???

[yilu@xxxxxxxxxxxxxx]

Hi,

If you use ISE6.3 with service pack 3 or higher version, there are offen some
par crashes in assemble stage with "fatal errors" or "segmental fault". Back to
ISE6.3 with service pack 2 or without patch, it should be working. It worked on
my system.

Regards,
yi lu

Quoting Philipp Reinkemeier <partial-reconfig@xxxxxxxxxxxx>:

> Philipp Reinkemeier schrieb:
> > Hello everyone
> >
> > I am trying to do DPR on a Virtex4, as i said earlier. Is there anyone
> > out there who did this before? I'm facing a lot of problems here and any
> > help would be great. I took Pete Sedcole's Slice based Macro and placed
> > it in a simple design: Just a static "hex2led" module and a
> > reconfigurable module "mult" and "add" which can be exchanged.
> >
> > Device: xc4vlx15 Package: ff668
> >
> > It seems that the xilinx tools don't give a **** about the constraints i
> > set. Here they are:
> >
> >
> >
> >
> >
> > INST "inst_hex2led" AREA_GROUP = "AG_inst_hex2led" ;
> > AREA_GROUP "AG_inst_hex2led" RANGE = SLICE_X4Y127:SLICE_X27Y0,
> > RAMB16_X0Y0:RAMB16_X0Y15, DSP48_X0Y0:DSP48_X0Y31,
> > FIFO16_X0Y0:FIFO16_X0Y15 ;
> > AREA_GROUP "AG_inst_hex2led" MODE = RECONFIG ;
> >
> > INST "inst_dyn" AREA_GROUP = "AG_inst_dyn" ;
> > AREA_GROUP "AG_inst_dyn" RANGE = SLICE_X28Y127:SLICE_X43Y0,
> > RAMB16_X1Y0:RAMB16_X1Y15, RAMB16_X2Y0:RAMB16_X2Y15,
> > FIFO16_X1Y0:FIFO16_X1Y15, FIFO16_X2Y0:FIFO16_X2Y15 ;
> > AREA_GROUP "AG_inst_dyn" MODE = RECONFIG ;
> >
> >
> > INST "inst_bm_v4_westeast_op" LOC = "SLICE_X24Y114" ;
> > INST "inst_bm_v4_westeast_rst" LOC = "SLICE_X24Y110" ;
> > INST "inst_bm_v4_eastwest_res" LOC = "SLICE_X24Y106" ;
> >
> >
> >
> >
> >
> >
> > When i want to route the design "par" routes a few signals across the
> > definied module boundaries (without any warning). It seems it doesn't
> > recognise the constraints at all.
> > Another hint for that is the output of "bitgen". When i run "bitgen -d
> > -w -l -m -g Persist:Yes -g ActiveReconfig:Yes ..." it says:
> >
> >
> >
> >
> >
> > Release 6.3.03i - Bitgen G.38
> > Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
> >
> > Loading device database for application Bitgen from file
> > "top_add_routed.ncd".
> >    "top_add" is an NCD, version 2.38, device xc4vlx15, package ff668,
> > speed -10
> > Loading device for application Bitgen from file '4vlx15.nph' in environment
> > C:/Xilinx.
> >
> > Thu Jun 01 00:59:38 2006
> >
> > Writing out a partial bitstream for module inst_dyn.
> > WARNING:Bitgen:221 - ActiveModule inst_dyn does not have a ROUTE_AREA
> > property.
> >
> >    The bitstream will be empty.
> > Saving ll file in "top_add_routed.ll".
> > Creating bit map...
> > Saving bit stream in "top_add_routed.bit".
> > Creating bit mask...
> > Saving mask bit stream in "top_add_routed.msk".
> > Bitstream generation is complete.
>
>
> A small update. This whole problem seems to be dependent on the device i
> used. I tried the same design on a xc2v1000 and voila: the bus macros
> worked as expected. No signal is routed across the boundary.
> Unfortunately in the final assembly stage par crashes without showing an
> error report.
>
>
> again
> help is greatly appreciated
>
> Philipp
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