Re: [partial-reconfig] PR module not on top level

["Love Singhal" <lovesinghal@xxxxxxxxx>]

Enno, 
If you have access to it, try using PlanAhead for this purpose. 
 Planahead could help in creation of area constraints for the lower blocks of hierarchy.

All the best,
Love Singhal

On 7/11/06, Enno Luebbers <enno.luebbers@xxxxxxxxxxxxxxxx> wrote:

Hi,

I'm trying to build a partially reconfigurable EDK system (EDK and ISE
8.1). I'm following the Early-Access Partial Reconfiguration Design Flow
6, which also has some comments about modifying an EDK design for
partial reconfiguration; essentially, they pipe the OPB bus signals
through bus macros.

However, I have an OPB peripheral (static) with connections to another
VHDL module (dynamic), which is instantiated in the user_logic.vhd of
the peripheral - so my PR module is in a lower level of the hierarchy
(say system_i/opb_mycore_0/opb_mycore_0/pr_module_inst; the opb_mycore_0
is in there twice because of the wrapper generated by EDK).

The problem is that if I try to define an AREA_GROUP for this
pr_module_inst in the UCF, the "Translate"-step of ISE complains that
there is no system_i/opb_mycore_0/opb_mycore_0/pr_module_inst - of
course it's hidden in the opb_mycore_0_wrapper that's already been
synthesized by EDK. On an unconstrained design, the FPGA-Editor shows
that I'm using the right name.

Is there a way to tell ISE to look inside pre-synthesized modules for
instance names?

Thanks for any help!

Best regards,
Enno

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