Re: [partial-reconfig] icap of Virtex-II Pro

2006/7/14, Gyorgy Horvath <horvaath@xxxxxxxxxxxxxxxxx>:

Dani Rguez wrote:
> Hi to everyone!
>
>  I´m new here. For what I read I think you have been working long with
> partial reconfiguration. I want to ask if anyone knows about the ICAP
> module. I found the intantiation template in XIlinx help, but no more.
> It does not even say if it is active low or high (I supose it will be
> active high for both WE and CE, but I just supose it). If anyone knows
> for sure, I will be thankful to answer, because it does nothing in any
> case. By the way, does anyone know what timing requirements are needed
> to write there? Any wait states needed? More than one cycle WE active?
>
>  Thank you very much for your help.
>
>  Daniel Rodriguez
>
>
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Hi,
I have Virtex4 and it's active low.
I thinks it's timing is much like DRP for GT's.
Timing spec said 50MHz or so for DRP. I run it on 30MHz for sure.
No Wait-States. There are NOP's in the bit-stream when it is necessary.
Also, when you see BUSY, keep the last word on the bus.
(I did not put my life on this :-)
Yes. More than one WE cycles. Long bursts allowed.
Warning! Did not change WE during CE. That is an abort.

Some notes:
- Read XAPP151, UG071, UG191 for a clear picture.
- Read the earlier posts :-)
- You may find hwicap in EDK. Check it out.
- You may try PlanAhead. Read the DOCs enclosed there.
- Did not try to program the device until you successfuly
read back at least the Xilinx Device ID, and the status register.
- Always sync-up before try
- Always issue a DESYNC command when you finished

Also, may the force be with you...

Gyuri

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