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Re: [partial-reconfig] icap of Virtex-II Pro

Hi,

Here's my code. It is for Virtex-4, and working fine.
Give it a try... but be careful.
Notes: - ulzag is a macro to manage the bit/byte order.
          - V4CTL_xxxxx codes are right from the book.
          - udelay is a macro - calls  KeStallExecutionProcessor
          - DUMMY is 0xFFFFFFFFLU
          - I did not know if Virtex2 has DESYNC or not
          - its a snip from the driver code for XP

/*  - Identify FPGA, and read status  */
     pAdapter->fpga->data[0] = ulzag( V4CTL_DUMMY    );
     pAdapter->fpga->data[1] = ulzag( V4CTL_SYNC     );
     pAdapter->fpga->data[2] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->data[3] = ulzag( V4CTL_RDIDCODE );
     pAdapter->fpga->data[4] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->data[5] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->data[6] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->cmd     = ICAP_WRITE | 6LU       ;
     udelay( 20L );
     pAdapter->fpga->cmd     = ICAP_READ  | 1LU       ;
     udelay( 20L );
     l = pAdapter->fpga->data[0];
     pAdapter->devid = ulzag(l);
     aprintf(  "[%i]FPGA Dev.ID.: (%.8lX)\n",
               pAdapter->No, pAdapter->devid );
     pAdapter->fpga->data[0] = ulzag( V4CTL_RDSTAT   );
     pAdapter->fpga->data[1] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->data[2] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->data[3] = ulzag( V4CTL_NOP      );
     pAdapter->fpga->cmd     = ICAP_WRITE | 4LU       ;
     udelay( 20L );
     pAdapter->fpga->cmd     = ICAP_READ  | 1LU       ;
     udelay( 20L );
     l = pAdapter->fpga->data[0];
     l = ulzag(l);
     aprintf(  "[%i]FPGA Status.: (%.8lX)\n",
               pAdapter->No, l );
     if( l&V4STA_CRC_ERROR     ) aprintf( "   + CRC_ERROR    \n" );
     if( l&V4STA_PART_SECURED  ) aprintf( "   + PART_SECURED \n" );
     if( l&V4STA_DCM_LOCK      ) aprintf( "   + DCM_LOCK     \n" );
     if( l&V4STA_DCI_MATCH     ) aprintf( "   + DCI_MATCH    \n" );
     if( l&V4STA_EOS           ) aprintf( "   + EOS          \n" );
     if( l&V4STA_GTS_CFG_B     ) aprintf( "   + GTS_CFG_B    \n" );
     if( l&V4STA_GWE           ) aprintf( "   + GWE          \n" );
     if( l&V4STA_GHIGH_B       ) aprintf( "   + GHIGH_B      \n" );
     if( l&V4STA_M0            ) aprintf( "   + M0           \n" );
     if( l&V4STA_M1            ) aprintf( "   + M1           \n" );
     if( l&V4STA_M2            ) aprintf( "   + M2           \n" );
     if( l&V4STA_INIT_COMPLETE ) aprintf( "   + INIT_COMPLETE\n" );
     if( l&V4STA_INIT          ) aprintf( "   + INIT         \n" );
     if( l&V4STA_RELEASE_DONE  ) aprintf( "   + RELEASE_DONE \n" );
     if( l&V4STA_DONE          ) aprintf( "   + DONE         \n" );
     if( l&V4STA_IO_ERROR      ) aprintf( "   + IO_ERROR     \n" );
     if( l&V4STA_DEC_ERROR     ) aprintf( "   + DEC_ERROR    \n" );
/*  - Desync. */
     pAdapter->fpga->data[0] = ulzag( V4CTL_WRCMD    );
     pAdapter->fpga->data[1] = ulzag( V4CMD_DESYNC   );
     pAdapter->fpga->cmd     = ICAP_WRITE | 2LU       ;


Ricardo Jardel Nunes da Silveira wrote:

Dear Dani,
Could you share same information (may be the code) about how did you get reading the id code ? I´m trying do it using the icap device driver under linux, but linux simply crash. 1. WRITE SYNC COMMAND 0xAA ... 
2. WRITE READ COMMAND 0X28 ...
3. WRITE NOOP COMMAND 0x20000000
4. WRITE NOOP COMMAND 0x20000000
5. READ FOUR BYTES: The id code!
6. WRITE DESYNC COMMAND 0x0000000D
7. WRITE NOOP COMMAND 0x20000000
8. WRITE NOOP COMMAND 0x20000000
Thanks. Jardel.
2006/7/21, Dani Rguez <rodherdan@xxxxxxxxxxx <mailto:rodherdan@xxxxxxxxxxx>>: 

    Hi again!

    First of all thank you for your advices. They were very helpful. After
    lots of problems with bit order and so (I know that now, of course
    :-) ) I
    am able to read the Device ID from y Virtxe-II Pro, but it gives an
    incorrect (ejem..) ID.

    The ID for Virtex-II Pro XC2VP30 is 0x0127E093 as it is said in
    ug012.pdf,
    but when I read that register I get 0x1127E093

    Just a number wrong. Very strange. And I watched a bitstream
    generated by
    ISE and when it writes the Device ID it puts the original one
    (0x0127...).

    Does anyone know why can this be? Is it normal? Maybe that nibble is
    "Don´t Care" and can be anything?? But I think no,  because I
    tried to write
    the ID with the new ID and the configuration failed. All
    suggestions are
    welcome.

    Greetings,

    Dani



    >From: Gyorgy Horvath <horvaath@xxxxxxxxxxxxxxxxx
    <mailto:horvaath@xxxxxxxxxxxxxxxxx>>
    >Reply-To: partial-reconfig@xxxxxxxxxxxxxx
    <mailto:partial-reconfig@xxxxxxxxxxxxxx>
    >To: partial-reconfig@xxxxxxxxxxxxxx
    <mailto:partial-reconfig@xxxxxxxxxxxxxx>
    >Subject: Re: [partial-reconfig] icap of Virtex-II Pro
    >Date: Fri, 14 Jul 2006 14:45:24 +0200
    >
    >Dani Rguez wrote:
    >>Hi to everyone!
    >>
    >>  I´m new here. For what I read I think you have been working
    long with
    >>partial reconfiguration. I want to ask if anyone knows about the
    ICAP
    >>module. I found the intantiation template in XIlinx help, but no
    more. It
    >>does not even say if it is active low or high (I supose it will
    be active
    >>high for both WE and CE, but I just supose it). If anyone knows
    for sure,
    >>I will be thankful to answer, because it does nothing in any
    case. By the
    >>way, does anyone know what timing requirements are needed to
    write there?
    >>Any wait states needed? More than one cycle WE active?
    >>
    >>  Thank you very much for your help.
    >>
    >>  Daniel Rodriguez
    >>
    >>
    >>___________________________
    >>partial-reconfig mailing list
    >>partial-reconfig@xxxxxxxxxxxxxx
    <mailto:partial-reconfig@xxxxxxxxxxxxxx>
    >>Mailing List Archive :
    >>http://www.itee.uq.edu.au/~listarch/partial-reconfig/
    <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>
    >Hi,
    >I have Virtex4 and it's active low.
    >I thinks it's timing is much like DRP for GT's.
    >Timing spec said 50MHz or so for DRP. I run it on 30MHz for sure.
    >No Wait-States. There are NOP's in the bit-stream when it is
    necessary.
    >Also, when you see BUSY, keep the last word on the bus.
    >(I did not put my life on this :-)
    >Yes. More than one WE cycles. Long bursts allowed.
    >Warning! Did not change WE during CE. That is an abort.
    >
    >Some notes:
    >- Read XAPP151, UG071, UG191 for a clear picture.
    >- Read the earlier posts :-)
    >- You may find hwicap in EDK. Check it out.
    >- You may try PlanAhead. Read the DOCs enclosed there.
    >- Did not try to program the device until you successfuly
    >  read back at least the Xilinx Device ID, and the status register.
    >- Always sync-up before try
    >- Always issue a DESYNC command when you finished
    >
    >Also, may the force be with you...
    >
    >Gyuri
    >
    >
    >
    >
    >___________________________
    >partial-reconfig mailing list
    >partial-reconfig@xxxxxxxxxxxxxx
    <mailto:partial-reconfig@xxxxxxxxxxxxxx>
    >Mailing List Archive :
    > http://www.itee.uq.edu.au/~listarch/partial-reconfig/
    <http://www.itee.uq.edu.au/%7Elistarch/partial-reconfig/>


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