[partial-reconfig] dpr on ise7.1/8.1/8.2

[Horea Coroiu <h230184@xxxxxxxxx>]

Hello all
I've been experimenting with modular design for two weeks now. I read all possible tutorials & papers but I couldn't found whether modular design is possible on any version of ise different from 6.3. My test project is very simple and works on ise 6.3.
On all other versions I get this error when I run map in the active module implementation stage
FATAL_ERROR:Pack:pktbamanager.c:1490:1.87.8.7 - Exception during DRC: The type ID name 'VCC_BLOCK' is not valid. 
It seems to be something related to the vcc/gnd signals that drive the 3 state buffers of the bus macro.
 I tried to generate vcc/gnd in the modules 
entity left is 
 Port (i : in std_logic_vector(3 downto 0);
      o : out std_logic_vector(3 downto 0));
    zero, one : out std_logic_vector(3 downto 0));
Another option was to write a bus macro with a lut that outputs vcc/gnd. 
and place it at a fixed position in the ucf.
Every time
 the error is the same.

The top design:
....
 righti: right port map (x => switch(1), y => switch(0), o => busin);
 lefti: left port map (i => busout, o => led);
 vccgndl: vccgnd port map (vcc => vccl, gnd => gndl);
 vccgndr: vccgnd port map (vcc => vccr, gnd => gndr);
 zerol <= (others => gndl); onel <= (others => vccl);
 zeror <= (others => gndr); oner <= (others => vccr);
 bus_macroi: bus_macro port map 
    (li => zerol, lt => zerol, 
     ri => busin, rt => oner, o => busout);
...

The ucf file (spartan 2) 
AREA_GROUP "lag" MODE=RECONFIG;
AREA_GROUP "rag" MODE=RECONFIG;

INST "vccgndl" LOC=CLB_R1C13.S0;
INST "vccgndr" LOC=CLB_R1C27.S0;

INST "vccgndl" LOCK_PINS;
INST "vccgndr" LOCK_PINS;

INST "lefti" AREA_GROUP = "lag";
AREA_GROUP "lag" RANGE =
 CLB_R1C1:CLB_R28C20;            
AREA_GROUP "lag" RANGE = TBUF_R1C1:TBUF_R28C20;
AREA_GROUP "lag" RANGE = RAMB4_R0C0:RAMB4_R6C0;
AREA_GROUP "lag" GROUP = CLOSED;
AREA_GROUP "lag" PLACE = CLOSED;

INST "righti" AREA_GROUP = "rag";
AREA_GROUP "rag" RANGE = CLB_R1C21:CLB_R28C42;
AREA_GROUP "rag" RANGE = TBUF_R1C21:TBUF_R28C42;
AREA_GROUP "rag" RANGE = RAMB4_R0C1:RAMB4_R6C1;
AREA_GROUP "rag" GROUP = CLOSED;
AREA_GROUP "rag" PLACE = CLOSED;

INST "bus_macroi" LOC = "TBUF_R1C17.0";

Pls those who have any clue hurry up, it's urgent ! :((

Notes
-Grégory Mermoud's design works perfectly on ise 6.3 and fails with "type ID name 'VCC_BLOCK' is not valid" at map on all other version.
-It seems nobody else had such problems as a google search for VCC_BLOCK' returns 0 results.
-If I remove the AREA_GROUP "lag" MODE=RECONFIG line from the ucf file
map works.

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