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RE: [partial-reconfig] Final Stage on Module-Based Partial Reconfig

Hi,

 I did that way the first time, so the error must be in otheer place.
The "Error" massages appear in the final assembly stage, when bitgen runs DRC. It says don´t exist some components an nets and when I look the .ncd just created by PAR with the FPGA Editor I see that effectively they are not there.
I send you those errors, but I think they are not very useful, since I think the problem lies before.
I send also other report files created in the process, just in case you want to see them. In .par it says 
"Guide : Placement Completed - errors found.
Guide : Routing Completed - errors found."

but I´m not able to find those errors.

 Thank you for your attention.

 Regards,

 Dani






From: yilu@xxxxxxxxxxxxxx
Reply-To: partial-reconfig@xxxxxxxxxxxxxx
To: partial-reconfig@xxxxxxxxxxxxxx
Subject: RE: [partial-reconfig] Final Stage on Module-Based Partial Reconfig 
Date: Fri, 04 Aug 2006 12:15:51 +1000

Hi,
The bus-macro.nmc is required by all these stages. From your information, I am not sure what happend on your system. Check all ucf files for your system see 
if they match. And could you please show us the error message?

regards,
yi lu

Quoting Dani Rguez <rodherdan@xxxxxxxxxxx>:

> Hi Michael,
>
> I didn´t mean in the vhdl code. I was speaking about putting or not the
> bus-macro in the folder when doing each stage. I had put it in all stages > and after your answer I tried putting it just in Initial and Assembly Stages > (those who inply the top entity), but I got the same result. After that I 
> have tried to do it just in the final assembly stage but it has problems
> too. In fact, when I try any stage without the nmc, it says I need
> AREA_GROUP constraint for the bus-macro, so I have to change the ucf for
> those cases, which goes against the rule that top.ucf must be the same for 
> all compilation.
>
>   When you say "MAP and PAR of the static part of the design need the
> related
> >bus_macroxxx.nmc to be copied to the local directory", do you mean that you 
> >use the .nmc just in that stage (the Active Module Implementation)? You
> >don´t put the .nmc in the folder when you do the same with the
> >reconfigurable modules??
>
> Can you please tell me in which stages you put it and when not? I supose > we both have the same 3 main stages: Initial, Active Module and Assembly. 
>
>   Thank you in advance,
>
>   Dani
>
>
>
> >From: "Michael Florian" <MFlorian@xxxxxxxxx>
> >Reply-To: partial-reconfig@xxxxxxxxxxxxxx
> >To: <partial-reconfig@xxxxxxxxxxxxxx>
> >Subject: RE: [partial-reconfig] Final Stage on Module-Based Partial
> >Reconfig
> >Date: Thu, 3 Aug 2006 08:45:09 +0100
> >
> >Hi Dani,
> >
> >what do you mean by "I used the Bus-Macro in all compilations"?
> >The Bus-Macro must be instantiated *only* in the top_level.vhd.
> >In the top_level.ucf, it must be loced to an appropriate slice.
> >MAP and PAR of the static part of the design need the related
> >bus_macroxxx.nmc to be copied to the local directory.
> >That actually works for me ;o)
> >
> >Regards,
> >Michael
> >
> >-----Original Message-----
> >From: owner-partial-reconfig@xxxxxxxxxxxxxx
> >[mailto:owner-partial-reconfig@xxxxxxxxxxxxxx]On Behalf Of Dani Rguez
> >Sent: Tuesday, August 01, 2006 6:16 PM
> >To: partial-reconfig@xxxxxxxxxxxxxx
> >Subject: [partial-reconfig] Final Stage on Module-Based Partial Reconfig 
> >
> >
> >   Hi,
> >
> > I´m trying to run the Module-Based flow for Partial Reconfiguration as 
> >explained in XAPP290.pdf.
> >
> > I followed all the indications step by step and after some problems I 
> >got
> >to the Final Assembly Stage. But there, I have some unbelievable problem: 
> >PAR takes the Bus-Macro out!! Bitgen fails in the DRC, finding a lot of
> >unplaced components and completely unrouted nets, all of them part of the > >Bus-Macro and when I looked back I found using the FPGA Editor that the > >Bus-Macro wasn´t in the last .ncd; there are both sides (the fixed side and 
> >the reconfigurable) but not the intermediate Bus-Macro.
> >
> >   Does anyone have this problem?
> >
> > I give more information (:-D : In the Active Module Phase, I used the > >Bus-Macro in all compilations with each module, because I think it must be 
> >said where to route the signals. That´s why in the Final Assembly Phase
> >both
> >sides (the 2 .ncd it takes for assembling) have in common the bus-macro. 
> >
> > Could it be that the problem?? I´m really lost. If anyone has a clue it 
> >will be welcome.
> >
> >   Thank you,
> >
> >   Dani
> >
> >
> >___________________________
> >partial-reconfig mailing list
> >partial-reconfig@xxxxxxxxxxxxxx
> >Mailing List Archive :
> >http://www.itee.uq.edu.au/~listarch/partial-reconfig/
> >
> >___________________________
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> >partial-reconfig@xxxxxxxxxxxxxx
> >Mailing List Archive :
> >http://www.itee.uq.edu.au/~listarch/partial-reconfig/
>
>
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>



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Release 8.1.03i - Bitgen I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '2vp30.nph' in environment 
C:\Xilinx8.1.
"top_opb_tornado_TBM_calcu" is an NCD, version 3.1, device xc2vp30, package 
ff896, speed -6
Opened constraints file top_opb_tornado_TBM_calcu.pcf.

Mon Jul 31 17:57:57 2006

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
Inst_fixed_side/Inst_wbm_uart/_n0020 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data 
  into the flip-flop.
ERROR:PhysDesignRules:10 - The network <FS_wb_ack_node> is completely unrouted. 
ERROR:PhysDesignRules:10 - The network <FS_reconf_ack_node> is completely
  unrouted.
ERROR:PhysDesignRules:9 - The network <CLKDV_OUT> is only partially routed.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<7>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<6>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<5>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<4>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<3>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<2>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<1>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_o_node<0>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_leds_node<7>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<6>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<5>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<4>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<3>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<2>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<1>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_leds_node<0>> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_wb_adr_node> is completely unrouted. ERROR:PhysDesignRules:9 - The network <FS_rst_node> is only partially routed. ERROR:PhysDesignRules:10 - The network <FS_wb_we_node> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_wb_stb_node> is completely unrouted. ERROR:PhysDesignRules:10 - The network <FS_stb_req_reconf_node> is completely 
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<7>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<6>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<5>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<4>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<3>> is completely
  unrouted.
ERROR:PhysDesignRules:10 - The network <FS_wb_dat_i_node<2>> is completely
  unrouted.
ERROR:PhysDesignRules:794 - Component Inst_fixed_side/Inst_fixed_side/O is not 
  placed.
ERROR:PhysDesignRules:794 - Component Inst_fixed_side/Inst_fixed_side/O1 is not 
  placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_RST_I is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFOUTPUT_BUS6 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFINPUT_BUS4 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFOUTPUT_BUS7 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFINPUT_BUS5 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFINPUT_BUS6 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TFINPUT_BUS7 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_STB is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_ACK is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_RECONF_ACK is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O0 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O1 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O2 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_ADR0 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O3 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O4 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O5 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O6 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TDOUTPUT_BUS0 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_LEDS_O0 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TD_LEDS_O7 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TDOUTPUT_BUS1 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_LEDS_O1 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TDOUTPUT_BUS2 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_LEDS_O2 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_STB is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TDOUTPUT_BUS3 is not placed.
ERROR:PhysDesignRules:794 - Component
  Inst_bus_macro_81_v03/Inst_bus_macro_81_v03/TF_LEDS_O3 is not placed.
ERROR:PhysDesignRules - <72> messages for unrouted networks were not reported. 
ERROR:PhysDesignRules - <35> unplaced comp messages were not reported.
ERROR:Bitgen:25 - DRC detected 167 errors and 1 warnings.

Attachment: top_opb_tornado_TBM_calcu.par
Description: Binary data

Attachment: top_opb_tornado_TBM_calcu.grf
Description: Binary data

Attachment: top_opb_tornado_TBM_calcu_map.mrp
Description: Binary data