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Re: [partial-reconfig] Re: [microblaze-uclinux] Adding bootloop to a bitstream made outside EDK
Thanks Pete,
Pete Sedcole wrote:
> ERROR:Data2MEM:89 - Unrecognized register address 10 in .bit file,
> 'static_full.bit'.
>
This sounds like a problem with the generated bit file. It could be
referring to a write to a non-existent configuration register. In the
Virtex II I think configuration register 10 is reserved.
In the log file, there seems to be several lines like the following:
> mpd line 67 - tool overriding c_family value virtex2 to
> microblaze (microblaze_0) -
> C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v5_00_a\data\microblaze_v2_1_0.
It seems that the device family is being set to nothing. What device are
you using? You'll need to make sure that the tool sets the family correctly.
I've checked and verified that ISE, EDK and PlanAhead are all using
the appropriate Virtex II Pro. I agree that it's probably the
bitstream, since futher attempt with bitinit syntax verified by John
continue to fail, but it does appear to be valid enough to program the
FPGA initially.
I have a partially reconfigurable design that works when built in
PlanAhead without the MicroBlaze and a MicroBlaze project that works
when generated in EDK. When combined together it appears that neither
work. The partially reconfigurable design is only a counter, but when
I push the increment button the counter does not increase (but the
numbers displays fine. I use the top level system.vhd file from EDK
and add it to my partial reconfiguration design. They are not
connected by bus macros because they do not interact. The MicroBlaze
is only on the FPGA to reconfigure the counter.
The one thing I can think of that I might be doing wrong it how I
remove the clock component wrappers and instantiate and connect the
clock primitives. The Early Access Partial Reconfiguration Guide
says:
"Clock primitives such as DCMs and BUFGs in PR systems must appear in
the top-level design entity; however, EDK places these primitives
within a wrapper entity (named dcm_module_0 by default). The wrapper
entity must be removed from the system (the component declaration and
instantiations can be commented out), and the requisite clock
primitives must be declared, instantiated, and wired into the system."
I took this to mean that I should comment out the dcm_0_wrapper and
dcm_1_wrapper component declarations like so;
-- component dcm_0_wrapper is
-- port (
-- RST : in std_logic;
-- CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- PSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSCLK : in std_logic;
-- DSSEN : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLKDV : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0);
-- LOCKED : out std_logic;
-- PSDONE : out std_logic
-- );
-- end component;
-- attribute box_type of dcm_0_wrapper: component is "black_box";
-- component dcm_1_wrapper is
-- port (
-- RST : in std_logic;
-- CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- PSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSCLK : in std_logic;
-- DSSEN : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLKDV : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0);
-- LOCKED : out std_logic;
-- PSDONE : out std_logic
-- );
-- end component;
--
-- attribute box_type of dcm_1_wrapper: component is "black_box";
--
And change the instantiation of dcm_0 and dcm_1 to
dcm_0 : dcm ## from dcm_0_wrapper
port map (
RST => net_gnd0,
CLKIN => dcm_clk_s,
CLKFB => sys_clk_s(0),
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => sys_clk_s(0),
CLK90 => clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
STATUS => open,
LOCKED => dcm_0_lock,
PSDONE => open
);
dcm_1 : dcm ## dcm_1_wrapper
port map (
RST => dcm_0_lock,
CLKIN => ddr_feedback_s,
CLKFB => dcm_1_FB,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => dcm_1_FB,
CLK90 => ddr_clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
STATUS => open,
LOCKED => open,
PSDONE => open
);
This synthesized in IDE, EDK and PlanAhead but in the only example I
could find (a PPC design) a new dcm component is declared. Do you
think this is valid, or could it be causing my problem?
Thanks for your help,
David
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