I've have had little success putting both the MicroBlaze and my
partial reconfiguration circuit on the same Virtex II-Pro. This
really is the last step before I can start testing some really
interesting methods for relocating cores in the Virtex II Pro
(provided I've installed John Williams drivers correctly). This for a
master's thesis which should wrap up in early January, but if I can't
get the Microblaze to work I may have to throw out much of the work I
have done this semester.
I'm hoping that by explaining the processing I am using here, someone
will be able to point out my fatal flaw. I continue to have the same
problem in 8.2 where data2mem crashed when I try to add the bootloop
to the bitstream.
I have been able to get 8.1 to produce a bitstream that I can add the
bootloop to but it crashes (ERROR:MDT – MicroBlaze Pipeline Stalled…)
after I load the image.bin file and start the MicroBlaze with XMD. It
also stalls if I add MemoryTest to the bitstream (and start a zero).
The bitstreams produced by EDK works fine so I don't think it's the
design of my Microblaze. Here's what I have to do to it to work using
EDK 8.1, ISE 8.1.01i_PR_8 and PlanAhead 8.2.2.
1. Create the system as usual using BSB.
2. Generate the netlist
3. Take the system.vhd file produced by EDK and add my static
portions, reconfigurable components and bus macros. Remove the DCM
wrappers component declarations and change the DCM wrapper instances
to DCM instances. Add I/O buffers for all of the pins using the
static portion of my reconfigurable circuit.
4. Update EDK's data/system.ucf file to include pins used by
static portion of reconfigurable circuit as well as LOC constraints
and I/O buffers. I have found that the GROUP/AREA information must be
included for PlanAhead design rule checks to pass (otherwise it thinks
that reconfigurable modules are connected to all pins).
5. Adjust system_xst.prj to the following (again required to get
PlanAhead to pass design rule checks). Normally iobuf is no, but
isn't it required for the top-level design?
run
-opt_mode speed
-opt_level 1
-p xc2vp30ff896-7
-top system
-ifmt MIXED
-ifn system_xst.prj
-ofn ../implementation/system.ngc
-hierarchy_separator /
-iobuf YES
-sd {../implementation}
6. Run xst –ifn system_xst.scr
7. Copy implementation/system.ngc to the /top directory of the
reconfigurable design.
8. Copy the ngc files for all other components of the MicroBlaze
in the implementation to the /base directory of the partial
reconfiguration design.
9. Create a new project in PlanAhead using top/system.ngc as the
top level file. Include the presynthesized static modules of the PR
design, the modules of the microblaze and one version of each
reconfigurable module in the netlist path.
10. Specify the FPGA.
11. Add a UCF file that contains all constraints.
12. Adjust any physical constraints that don't pass the PlanAhead
design rules. This usually includes placement of DCM and BUFGs.
13. Run the partial reconfiguration process in PlanAhead using the
default settings
14. Take the static_full.bit file produced and add the bootloop
using bitinit
15. Use XMD to download image.bin and start the processor.
All I've had to work on is the limited instructions for adding an EDK
design to a partial reconfiguration design on the Xilinx Early Access
PR website. Does anyone know of a better source for instructions?
I've attached my system.vhd and the UCF file from PlanAhead which is
also used in xst in case someone can find the time to look that them.
Your help is very much appreciated,
Dav
id