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Re: [partial-reconfig] Integrating Microblaze in PR design
John,
Thank you for the reply.
Actually I don't believe have a mixed tool situation. Since I had
trouble in 8.2, I've also tried to get the system to work in both 8.1
and 8.2, but I have been very careful to reconstruct everything (other
than vhdl) in each of the tool chains. PlanAhead 8.2 is supposed to
work with all versions of ISE. I have used the subversions (8.2.4
with ISE 8.2 and 8.2.2 with ISE 8.1) recommended for the versions of
ISE that have partial reconfiguration patches.
I now believe that I have a bigger problem with the MicroBlaze. I
tried manually downloading elf files to the board as you suggest. When
I download the memory app to 0x00000000 and con, I get the following:
Starting MemoryTest for DDR_256MB_32MX64_rank1_row13_col10_cl2_5:
Running 32-bit test...-- Entering main() --
The processor hangs and can no longer be reached through XMD. When I
type stop, I get the following:
Unable to stop processor
Unable to Stop MicroBlaze
MicroBlaze Pipeline Stalled executing Instruction at >> PC: 000004f4,
MSR: 0x00000a0
This appears to be in the .text section of the program. I followed
this up by doing the simple act of writing and reading from memory.
Here are the results.
XMD% dis 0x4e0 20
4E0: 32C00001 addik r22, r0 , 1
4E4: 22400000 addi r18, r0 , 0
4E8: 165B9003 cmpu r18, r27, r18
4EC: BEB2002C bgeid r18, 44
4F0: 12600000 addk r19, r0 , r0
4F4: 107A0000 addk r3 , r26, r0
4F8: E8830000 lwi r4 , r3 , 0
4FC: 16562000 rsubk r18, r22, r4
500: BE3200BC bneid r18, 188
504: 32730001 addik r19, r19, 1
508: 32D60001 addik r22, r22, 1
50C: 165B9803 cmpu r18, r27, r19
510: BE52FFE8 bltid r18, -24
514: 30630004 addik r3 , r3 , 4
518: BE39FE84 bneid r25, -380
51C: 10600000 addk r3 , r0 , r0
520: 13800000 addk r28, r0 , r0
524: 33A00001 addik r29, r0 , 1
528: 331A007C addik r24, r26, 124
52C: 127A0000 addk r19, r26, r0
XMD% dis 0x0000000 20
0: B8080050 brai 80
4: 00000000 add r0 , r0 , r0
8: B80802A4 brai 676
C: 00000000 add r0 , r0 , r0
10: B80802B4 brai 692
14: 00000000 add r0 , r0 , r0
18: 00000000 add r0 , r0 , r0
1C: 00000000 add r0 , r0 , r0
20: B80802AC brai 684
24: 00000000 add r0 , r0 , r0
28: 00000000 add r0 , r0 , r0
2C: 00000000 add r0 , r0 , r0
30: 00000000 add r0 , r0 , r0
34: 00000000 add r0 , r0 , r0
38: 00000000 add r0 , r0 , r0
3C: 00000000 add r0 , r0 , r0
40: 00000000 add r0 , r0 , r0
44: 00000000 add r0 , r0 , r0
48: 00000000 add r0 , r0 , r0
4C: 00000000 add r0 , r0 , r0
XMD% dow executable.elf 0x30000000
XMD% dis 0x30000000 20
30000000: 30000000 addik r0 , r0 , 0
30000004: 30000000 addik r0 , r0 , 0
30000008: 30000000 addik r0 , r0 , 0
3000000C: 30000000 addik r0 , r0 , 0
30000010: 30000000 addik r0 , r0 , 0
30000014: 30000000 addik r0 , r0 , 0
30000018: 30000000 addik r0 , r0 , 0
3000001C: 30000000 addik r0 , r0 , 0
30000020: 30000000 addik r0 , r0 , 0
30000024: 30000000 addik r0 , r0 , 0
30000028: 30000000 addik r0 , r0 , 0
3000002C: 30000000 addik r0 , r0 , 0
30000030: 30000000 addik r0 , r0 , 0
30000034: 30000000 addik r0 , r0 , 0
30000038: 30000000 addik r0 , r0 , 0
3000003C: 30000000 addik r0 , r0 , 0
30000040: 30000000 addik r0 , r0 , 0
30000044: 30000000 addik r0 , r0 , 0
30000048: 30000000 addik r0 , r0 , 0
3000004C: 30000000 addik r0 , r0 , 0
XMD% stop
Unable to stop processor
Unable to Stop MicroBlaze
Verify if FPGA is configured and MicroBlaze System Clock is connected properly
---
Obviously this is not the desired or expected result. It appears that
I can not successfully read to or write from main memory.
Using PlanAhead there are actually only a few places for me to make a
mistake. First, I must manually instantiate the DCMs used by the
MicroBlaze. EDK uses wrappers from most of the components including
the DCMs, but for partial reconfiguration all DCMs must be part of the
top level design. To meet the design rules, I comment out the
component declarations from the wrappers and just change component
name of the DCMs from dcm_wrapper to dcm. Next, when using PlanAhead,
I must manually LOC the DMCs and BUFGs for the clocks including the
DDR and system clocks.
My last post included both the top level VHDL and UCF file which has
all placements and PlanAhead constraints. Hopefully someone will find
these helpful or will be able to point out a mistake in them.
Thanks,
David
On 12/5/06, John Williams <jwilliams@xxxxxxxxxxxxxx> wrote:
Hi David,
I'm sorry to hear you are having such a hard time with this. PlanAhead
is supposed to make PR "just work", but it sounds like you are just
jumping through a set of different, but equally painful hoops that I
went through 3 years ago. That was the reason I put this stuff aside
after demonstrating the ICAP driver with manually-created fpga_editor
"blinkenled" partial bitstreams.
It's also the reason I tell any of our students even considering
dynamic/partial reconfig work to forget about it. If they have enough
persistence to convince me otherwise, then maybe they have enough to
deal with the hassles that go with it!
Enough whining from me - scanning your description of the issue I can't
help but be scared by a mixing of 8.1 and 8.2 tools. I realise you had
issues with bitinit/data2mem in 8.2 - maybe that is the best problem to
be tackled, since it can be most neatly "captured" and duplicated (e.g.
in a webcase - see below).
In the mixed tool situation - When you get microblaze pipeline stalls
can you issue the XMD reset "rst" command, then use the 'dow' command to
load a new ELF image?
Have you been able to use XMD to manually drive the various bits of the
design - read/write the DDR, put characters out the uart, that sort of
thing?
Similarly can you run the various TestApp_XXXX standalone apps generated
by EDK?
In terms of where to go for help, are there any official support
channels for PlanAhead?
It sounds crazy, but have you considered raising a webcase? There seems
to be a shift at Xilinx recently whereby things must have a webcase
before anyone can act - perhaps its an attempt to accurately measure
support effort or something, I'm not sure.
My best suggestion is probably to wrap up your 8.2-generated bitstreams
and ELF files etc into an easy-to-reproduce failure report for data2mem.
Cheers
John
David Montminy wrote:
> I've have had little success putting both the MicroBlaze and my
> partial reconfiguration circuit on the same Virtex II-Pro. This
> really is the last step before I can start testing some really
> interesting methods for relocating cores in the Virtex II Pro
> (provided I've installed John Williams drivers correctly). This for a
> master's thesis which should wrap up in early January, but if I can't
> get the Microblaze to work I may have to throw out much of the work I
> have done this semester.
>
> I'm hoping that by explaining the processing I am using here, someone
> will be able to point out my fatal flaw. I continue to have the same
> problem in 8.2 where data2mem crashed when I try to add the bootloop
> to the bitstream.
>
> I have been able to get 8.1 to produce a bitstream that I can add the
> bootloop to but it crashes (ERROR:MDT – MicroBlaze Pipeline Stalled…)
> after I load the image.bin file and start the MicroBlaze with XMD. It
> also stalls if I add MemoryTest to the bitstream (and start a zero).
> The bitstreams produced by EDK works fine so I don't think it's the
> design of my Microblaze. Here's what I have to do to it to work using
> EDK 8.1, ISE 8.1.01i_PR_8 and PlanAhead 8.2.2.
>
> 1. Create the system as usual using BSB.
>
> 2. Generate the netlist
>
> 3. Take the system.vhd file produced by EDK and add my static
> portions, reconfigurable components and bus macros. Remove the DCM
> wrappers component declarations and change the DCM wrapper instances
> to DCM instances. Add I/O buffers for all of the pins using the
> static portion of my reconfigurable circuit.
>
> 4. Update EDK's data/system.ucf file to include pins used by
> static portion of reconfigurable circuit as well as LOC constraints
> and I/O buffers. I have found that the GROUP/AREA information must be
> included for PlanAhead design rule checks to pass (otherwise it thinks
> that reconfigurable modules are connected to all pins).
>
> 5. Adjust system_xst.prj to the following (again required to get
> PlanAhead to pass design rule checks). Normally iobuf is no, but
> isn't it required for the top-level design?
>
> run
> -opt_mode speed
> -opt_level 1
> -p xc2vp30ff896-7
> -top system
> -ifmt MIXED
> -ifn system_xst.prj
> -ofn ../implementation/system.ngc
> -hierarchy_separator /
> -iobuf YES
> -sd {../implementation}
>
> 6. Run xst –ifn system_xst.scr
>
> 7. Copy implementation/system.ngc to the /top directory of the
> reconfigurable design.
>
> 8. Copy the ngc files for all other components of the MicroBlaze
> in the implementation to the /base directory of the partial
> reconfiguration design.
>
> 9. Create a new project in PlanAhead using top/system.ngc as the
> top level file. Include the presynthesized static modules of the PR
> design, the modules of the microblaze and one version of each
> reconfigurable module in the netlist path.
>
> 10. Specify the FPGA.
>
> 11. Add a UCF file that contains all constraints.
>
> 12. Adjust any physical constraints that don't pass the PlanAhead
> design rules. This usually includes placement of DCM and BUFGs.
>
> 13. Run the partial reconfiguration process in PlanAhead using the
> default settings
>
> 14. Take the static_full.bit file produced and add the bootloop
> using bitinit
>
> 15. Use XMD to download image.bin and start the processor.
>
> All I've had to work on is the limited instructions for adding an EDK
> design to a partial reconfiguration design on the Xilinx Early Access
> PR website. Does anyone know of a better source for instructions?
> I've attached my system.vhd and the UCF file from PlanAhead which is
> also used in xst in case someone can find the time to look that them.
>
> Your help is very much appreciated,
>
> Dav
> id
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