Re: [partial-reconfig] Integrating Microblaze in PR design

["David Montminy" <dpmontminy@xxxxxxxxx>]

As a follow up,

I have been able to successfully integrate the MicroBlaze into a PR
design produced by PlanAhead.  The Xilinx's partial reconfiguration
documentation doesn't have much detail on what needs to be changed
when unwrapping the DCM from the DCM wrapper produced in PlanAhead, so
I'll expand on it here.

The key is to determine exactly what settings are captured by the
wrapper and which VHDL modules are used by the wrapper.  The wrapper
is located in the {EDK project)/vhd directory and contains all of the
settings for the DMC primitives.  The wrapper actually applies the
settings to a VHDL module called 'dcm_module' which properly chooses
the correct DCM primitive depending on the device and can add
inverters and buffers the DCM.  The partial reconfiguration top level
VHDL modules must account for all of the settings for the DCM as well
as any inverters and BUFGs added by dcm_module.

I hope this saves someone a headache!

David
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