[partial-reconfig] Spartan-3/3E partial reconfiguration

[Justin Braun <justin.braun@xxxxxxxxxxxxx>]

This group seems relatively inactive recently but I thought I would try 
to post a few questions about partial reconfiguration on the 
Spartan-3/3E series devices.

I recently went through the design flow as described in the Early Access 
Partial Reconfiguration User Guide. I had no problems making a small 
demo work on two separate Virtex-4 development boards but I could not 
successfully generate working bitstreams for the a Spartan-3E device. 
There were no errors until I started to generate the bitsreams. The 
pr_verifydesign step would generate "frame boundary errors" in the 
".summary" output file which Xilinx states:

"Frame boundary errors are likely due to illegal range constraints for 
the PR region. For
example, this error occurs if the BRAM range does not match the CLB 
range. Check to
ensure that the BRAM range includes all the block RAM elements within 
the CLB range."

My PR region only contains CLBs and there were no other errors 
throughout the process.

Is anybody doing partial reconfiguration on Spartan 3/3E devices?
How can I fix these "frame boundary errors"?

Some information on Xilinx's site about partial reconfiguration on 
Spartan-3/3E devices has stated, "unmodified bits in a partially 
reconfigured column in Spartan-3/-3E devices are temporarily reset 
during the reconfiguration process." Is this valid?

Thanks,
Justin Braun



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